Cypress CY7C1546V18, CY7C1557V18 manual CY7C1548V18 4M x, CY7C1550V18 2M x

Page 5

CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Pin Configuration (continued)

The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow. [2]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1548V18 (4M x 18)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

CQ

R/W

BWS1

K

NC/144M

LD

A

A

CQ

B

NC

DQ9

NC

A

NC/288M

K

0

A

NC

NC

DQ8

BWS

C

NC

NC

NC

VSS

A

NC

A

VSS

NC

DQ7

NC

D

NC

NC

DQ10

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ11

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ6

F

NC

DQ12

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

NC

DQ13

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ4

NC

K

NC

NC

DQ14

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ3

L

NC

DQ15

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

DQ1

NC

N

NC

NC

DQ16

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ17

A

A

QVLD

A

A

NC

NC

DQ0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

CY7C1550V18 (2M x 36)

1

2

3

4

5

6

7

8

9

10

11

A

NC/144M

A

CQ

R/W

BWS2

K

BWS1

LD

A

A

CQ

B

NC

DQ27

DQ18

A

3

K

0

A

NC

NC

DQ8

BWS

BWS

C

NC

NC

DQ28

VSS

A

NC

A

VSS

NC

DQ17

DQ7

D

NC

DQ29

DQ19

VSS

VSS

VSS

VSS

VSS

NC

NC

DQ16

E

NC

NC

DQ20

VDDQ

VSS

VSS

VSS

VDDQ

NC

DQ15

DQ6

F

NC

DQ30

DQ21

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ5

G

NC

DQ31

DQ22

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

DQ14

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

DQ32

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ13

DQ4

K

NC

NC

DQ23

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ12

DQ3

L

NC

DQ33

DQ24

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

M

NC

NC

DQ34

VSS

VSS

VSS

VSS

VSS

NC

DQ11

DQ1

N

NC

DQ35

DQ25

VSS

A

A

A

VSS

NC

NC

DQ10

P

NC

NC

DQ26

A

A

QVLD

A

A

NC

DQ9

DQ0

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

Document Number: 001-06550 Rev. *E

Page 5 of 28

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1557V18 Logic Block Diagram CY7C1546V18Logic Block Diagram CY7C1550V18 Logic Block Diagram CY7C1548V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1546V18 8M x CY7C1557V18 8M xCY7C1550V18 2M x CY7C1548V18 4M xPin Name Pin Description Pin DefinitionsBWS BWS2, BWS3 Synchronous Read or Write Input. WhenPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Valid Data Indicator QvldEcho Clocks SRAM#1 SRAM#2Operation Write Cycle DescriptionsBWS0 BWS1 CommentsBWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit Number Bump ID Power Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence 29, 30, 31 Switching WaveformsNOP Read NOP WriteOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN No Issue Orig. Description of Change DateDocument History