Cypress CY7C1546V18 Application Example, Echo Clocks, Valid Data Indicator Qvld, SRAM#1 SRAM#2

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CY7C1546V18, CY7C1557V18 CY7C1548V18, CY7C1550V18

Echo Clocks

Echo clocks are provided on the DDR-II+ to simplify data capture on high-speed systems. Two echo clocks are generated by the DDR-II+. CQ is referenced with respect to K and CQ is refer- enced with respect to K. These are free-running clocks and are synchronized to the input clock of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on page 23.

Valid Data Indicator (QVLD)

QVLD is provided on the DDR-II+ to simplify data capture on high speed systems. The QVLD is generated by the DDR-II+ device along with data output. This signal is also edge aligned with the echo clock and follows the timing of any data pin. This signal is asserted half a cycle before valid data arrives.

DLL

These chips use a Delay Lock Loop (DLL) that is designed to function between 120 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device behaves in DDR-I mode (with 1.0 cycle latency and a longer access time). For more information, refer to the application note, “DLL Consid- erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be reset by slowing or stopping the input clocks K and K for a minimum of 30ns. However, it is not necessary to reset the DLL to lock to the desired frequency. During Power-up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock.

Application Example

Figure 1 shows two DDR-II+ used in an application.

Figure 1. Application Example

 

 

 

SRAM#1

 

ZQ

 

 

SRAM#2

 

ZQ

 

 

 

DQ

CQ/CQ

R = 250ohms

DQ

CQ/CQ

R = 250ohms

 

 

 

 

 

 

 

 

A

LD

R/W

K

K

 

A

LD

R/W

K

K

 

 

 

DQ

 

 

 

 

 

 

 

 

 

 

 

BUS

 

Addresses

 

 

 

 

 

 

 

 

 

 

 

MASTER

Cycle Start

 

 

 

 

 

 

 

 

 

 

 

(CPU or ASIC)

R/W

 

 

 

 

 

 

 

 

 

 

 

 

Source CLK

 

 

 

 

 

 

 

 

 

 

 

 

Source CLK

 

 

 

 

 

 

 

 

 

 

 

Echo Clock1/Echo Clock1

 

 

 

 

 

 

 

 

 

 

 

Echo Clock2/Echo Clock2

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-06550 Rev. *E

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1557V18 Logic Block Diagram CY7C1546V18Logic Block Diagram CY7C1550V18 Logic Block Diagram CY7C1548V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1546V18 8M x CY7C1557V18 8M xCY7C1550V18 2M x CY7C1548V18 4M xPin Name Pin Description Pin DefinitionsBWS BWS2, BWS3 Synchronous Read or Write Input. WhenPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Valid Data Indicator QvldEcho Clocks SRAM#1 SRAM#2Operation Write Cycle DescriptionsBWS0 BWS1 CommentsBWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit Number Bump ID Power Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence 29, 30, 31 Switching WaveformsNOP Read NOP WriteOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramECN No Issue Orig. Description of Change Date Document HistoryREV
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