Cypress CY7C1557V18, CY7C1548V18, CY7C1546V18, CY7C1550V18 manual BWS0 BWS1 BWS2 BWS3

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CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Write Cycle Descriptions

The write cycle description table for CY7C1557V18 follows. [3, 9]

BWS0

K

K

Comments

L

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L

L–H

During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

Write Cycle Descriptions

The write cycle description table for CY7C1550V18 follows. [3, 9]

 

BWS0

 

BWS1

 

BWS2

 

BWS3

K

 

K

Comments

 

L

 

L

 

L

 

L

L–H

 

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

 

 

 

 

 

 

 

 

 

 

 

L

 

L

 

L

 

L

L–H

During the data portion of a write sequence, all four bytes (D[35:0]) are written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

L

 

H

 

H

 

H

L–H

 

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

L

 

H

 

H

 

H

L–H

During the data portion of a write sequence, only the lower byte (D[8:0]) is written

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

into the device. D[35:9] remains unaltered.

 

H

 

L

 

H

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remain unaltered.

 

H

 

L

 

H

 

H

L–H

During the data portion of a write sequence, only the byte (D[17:9]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[8:0] and D[35:18] remain unaltered.

 

H

 

H

 

L

 

H

L–H

 

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remain unaltered.

 

H

 

H

 

L

 

H

L–H

During the data portion of a write sequence, only the byte (D[26:18]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[17:0] and D[35:27] remain unaltered.

 

H

 

H

 

H

 

L

L–H

 

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

L

L–H

During the data portion of a write sequence, only the byte (D[35:27]) is written into

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the device. D[26:0] remains unaltered.

 

H

 

H

 

H

 

H

L–H

 

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

H

 

H

 

H

 

H

L–H

No data is written into the device during this portion of a write operation.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-06550 Rev. *E

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1557V18 Logic Block Diagram CY7C1546V18Logic Block Diagram CY7C1550V18 Logic Block Diagram CY7C1548V18CY7C1557V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1546V18 8M xCY7C1550V18 2M x CY7C1548V18 4M xSynchronous Read or Write Input. When Pin DefinitionsPin Name Pin Description BWS BWS2, BWS3TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview SRAM#1 SRAM#2 Valid Data Indicator QvldApplication Example Echo ClocksComments Write Cycle DescriptionsOperation BWS0 BWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit Number Bump ID DLL Constraints Power Up Sequence in DDR-II+ SramPower Up Waveforms Power Up SequenceRange Ambient Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceAC Test Loads and Waveforms AC Test Loads and WaveformsDLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead NOP Write Switching WaveformsRead/Write/Deselect Sequence 29, 30, 31 NOPOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN No Issue Orig. Description of Change DateDocument History