Cypress CY7C1550V18, CY7C1548V18 manual Pin Definitions, Pin Name Pin Description, BWS BWS2, BWS3

Page 6

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1546V18, CY7C1557V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1548V18, CY7C1550V18

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Definitions

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin Name

IO

 

 

 

 

 

Pin Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DQ[x:0]

Input and

Data Input or Output Signals. Inputs are sampled on the rising edge of K and

 

clocks during valid

 

K

 

 

 

 

 

 

 

 

 

 

 

 

 

Output

write operations. These pins drive out the requested data during a read operation. Valid data is driven

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

out on the rising edge of both the K and K clocks during read operations. When read access is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

deselected, Q[x:0] are automatically tri-stated.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1546V18 DQ[7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1557V18 DQ[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1548V18 DQ[17:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1550V18 DQ[35:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Synchronous Load. Sampled on the rising edge of the K clock. This input is brought LOW when a

 

LD

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

bus cycle sequence is defined. This definition includes address and read or write direction. All trans-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

actions operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,

 

 

 

1

Input

Nibble Write Select 0, 1 Active LOW (CY7C1546V18 only). Sampled on the rising edge of the K

 

NWS

NWS

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

and K clocks during write operations. Used to select the nibble that is written into the device during

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the current portion of the write operations. Nibbles not written remain unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NWS0 controls D[3:0] and NWS1 controls D[7:4].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Select ignores the corresponding nibble of data and does not write into the device.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0,

 

 

1,

Input

Byte Write Select 0, 1, 2, and 3 Active LOW. Sampled on the rising edge of the K and

 

clocks

 

BWS

BWS

K

 

BWS2, BWS3

Synchronous

during write operations. Used to select the byte written into the device during the current portion of

 

 

 

 

 

 

 

 

 

 

 

 

 

 

the write operations. Bytes not written remain unaltered.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1557V18 BWS0

controls D[8:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1548V18 BWS0

controls D[8:0] and

BWS

1 controls D[17:9].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CY7C1550V18 BWS0

controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

controls D[35:27].

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ignores the corresponding byte of data and does not write into the device.

 

 

 

 

 

A

Input

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

These address inputs are multiplexed for both read and write operations. Internally, the device is

 

 

 

 

 

 

 

 

 

 

 

 

 

 

organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1546V18, 8M x 9 (2 arrays each of 4M x 9)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

for CY7C1557V18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1548V18, and 2M x 36 (2 arrays

 

 

 

 

 

 

 

 

 

 

 

 

 

 

each of 1M x 36) for CY7C1550V18.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Synchronous Read or Write Input. When

 

is LOW, this input designates the access type (read

 

R/W

LD

 

 

 

 

 

 

 

 

 

 

 

 

 

Synchronous

when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold

 

 

 

 

 

 

 

 

 

 

 

 

 

 

times around edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

QVLD

Valid output

Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

 

 

 

 

 

 

 

 

 

 

 

 

 

indicator

CQ.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

K

Input

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising

 

 

 

 

 

 

 

 

 

 

 

 

 

 

edge of K.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

Negative Input Clock Input.

 

is used to capture synchronous data presented to the device and to

 

K

K

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock

drive out data through Q[x:0] when in single clock mode.

 

CQ

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clock (K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on

 

 

 

 

 

 

 

 

 

 

 

 

 

 

page 23.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Clock Output

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

 

CQ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

clock (K) of the DDR-II+. The timing for the echo clocks is shown in Switching Characteristics on

 

 

 

 

 

 

 

 

 

 

 

 

 

 

page 23.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document Number: 001-06550 Rev. *E

Page 6 of 28

[+] Feedback

Image 6
Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1546V18 Logic Block Diagram CY7C1557V18Logic Block Diagram CY7C1548V18 Logic Block Diagram CY7C1550V18CY7C1546V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1557V18 8M xCY7C1548V18 4M x CY7C1550V18 2M xBWS BWS2, BWS3 Pin DefinitionsPin Name Pin Description Synchronous Read or Write Input. WhenTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Echo Clocks Valid Data Indicator QvldApplication Example SRAM#1 SRAM#2BWS0 BWS1 Write Cycle DescriptionsOperation CommentsBWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBit Number Bump ID Power Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Range AmbientThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingNOP Switching WaveformsRead/Write/Deselect Sequence 29, 30, 31 Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 15 x 17 x 1.4 mmECN No Issue Orig. Description of Change Date Document HistoryREV