Cypress CY7C1548V18 manual Pin Configuration, Ball Fbga 15 x 17 x 1.4 mm Pinout, CY7C1546V18 8M x

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CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Pin Configuration

The pin configuration for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follow. [2]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1546V18 (8M x 8)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

CQ

R/W

NWS1

K

NC/144M

LD

A

A

CQ

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

NWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

QVLD

A

A

NC

NC

NC

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

CY7C1557V18 (8M x 9)

1

2

3

4

5

6

7

8

9

10

11

A

A

A

NC

NC/144M

A

A

CQ

CQ

R/W

K

LD

B

NC

NC

NC

A

NC/288M

K

0

A

NC

NC

DQ3

BWS

C

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

D

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

E

NC

NC

DQ4

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ2

F

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

G

NC

NC

DQ5

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

H

VREF

VDDQ

VDDQ

VDD

VSS

VDD

VDDQ

VDDQ

VREF

ZQ

DOFF

J

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

DQ1

NC

K

NC

NC

NC

VDDQ

VDD

VSS

VDD

VDDQ

NC

NC

NC

L

NC

DQ6

NC

VDDQ

VSS

VSS

VSS

VDDQ

NC

NC

DQ0

M

NC

NC

NC

VSS

VSS

VSS

VSS

VSS

NC

NC

NC

N

NC

NC

NC

VSS

A

A

A

VSS

NC

NC

NC

P

NC

NC

DQ7

A

A

QVLD

A

A

NC

NC

DQ8

R

TDO

TCK

A

A

A

NC

A

A

A

TMS

TDI

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

Document Number: 001-06550 Rev. *E

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Contents Features ConfigurationsFunctional Description Selection GuideLogic Block Diagram CY7C1546V18 Logic Block Diagram CY7C1557V18Logic Block Diagram CY7C1548V18 Logic Block Diagram CY7C1550V18Pin Configuration Ball Fbga 15 x 17 x 1.4 mm PinoutCY7C1546V18 8M x CY7C1557V18 8M xCY7C1548V18 4M x CY7C1550V18 2M xPin Definitions Pin Name Pin DescriptionBWS BWS2, BWS3 Synchronous Read or Write Input. WhenPower Supply Inputs to the Core of the Device Power Supply Inputs for the Outputs of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Valid Data Indicator Qvld Application ExampleEcho Clocks SRAM#1 SRAM#2Write Cycle Descriptions OperationBWS0 BWS1 CommentsBWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTAP Controller Block Diagram TAP Electrical CharacteristicsTDI TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsIdentification Register Definitions Scan Register SizesInstruction Codes Register Name Bit SizeBit Number Bump ID Power Up Sequence in DDR-II+ Sram Power Up WaveformsPower Up Sequence DLL ConstraintsElectrical Characteristics DC Electrical CharacteristicsMaximum Ratings Range AmbientAC Electrical Characteristics CapacitanceThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsSwitching Characteristics Cypress Consortium Description 375 MHz 333 MHz 300 MHz UnitParameter Min Max DLL TimingSwitching Waveforms Read/Write/Deselect Sequence 29, 30, 31NOP Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 15 x 17 x 1.4 mmDocument History ECN No Issue Orig. Description of Change DateREV