Cypress CY7C1548V18 manual Document History, Rev, ECN No Issue Orig. Description of Change Date

CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Document History Page

Document Title: CY7C1546V18/CY7C1557V18/CY7C1548V18/CY7C1550V18, 72-Mbit DDR-II+ SRAM 2-Word Burst Architec- ture (2.0 Cycle Read Latency)

Document Number: 001-06550

REV.	ECN No.	Issue	Orig. of	Description of Change
		Date	Change
**	432718	See ECN	NXR	New datasheet
*A	437000	See ECN	IGS	ECN for show on web
*B	461934	See ECN	NXR	Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH
				from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching
				Characteristics table
				Modified Power up waveform
*C	497567	See ECN	NXR	Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, Operating
				Range table, and the DC Electrical Characteristics table
				Added foot note in page 1
				Changed the Maximum rating of ambient temperature with power applied from –10°C
				to +85°C to –55°C to +125°C
				Changed VREF (Max) specification from 0.85V to 0.95V in the DC Electrical Character-
				istics table and in the note below the table
				Updated footnote 18 to specify overshoot and undershoot specifications
				Updated IDD and ISB values
				Updated ΘJA and ΘJC values
				Removed x9 part and its related information
				Updated footnote 25
*D	1351504	See ECN	VKN/AESA	Converted from preliminary to final
				Added x8 and x9 parts
				Updated logic block diagram for x18 and x36 parts
				Changed tCYC max spec to 8.4 ns for all speed bins
				Updated footnote# 21
				Updated Ordering Information table
*E	2193266	See ECN	VKN/AESA	Added footnote# 20 related to IDD

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Document Number: 001-06550 Rev. *E Revised March 11, 2008 Page 28 of 28

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document are the trademarks of their respective holders.

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