Cypress CY7C1557V18 manual TDO for Jtag, TCK Pin for Jtag, TDI Pin for Jtag, TMS Pin for Jtag

Page 7

 

 

 

 

 

 

CY7C1546V18, CY7C1557V18

 

 

 

 

 

 

CY7C1548V18, CY7C1550V18

 

 

 

 

 

 

Pin Definitions (continued)

 

 

 

 

 

 

 

Pin Name

IO

 

 

Pin Description

 

 

 

 

 

ZQ

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

 

 

 

 

bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor

 

 

 

 

connected between ZQ and ground. Alternatively, this pin is connected directly to VDDQ and enables

 

 

 

 

the minimum impedance mode. This pin is not connected directly to GND or left unconnected.

 

 

 

 

 

 

 

 

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The

 

DOFF

 

 

 

 

timing in the DLL turned off operation is different from that listed in this datasheet. For normal

 

 

 

 

operation, this pin is connected to a pull up through a 10 Kohm or less pull up resistor. The device

 

 

 

 

behaves in DDR-I mode when the DLL is turned off. In this mode, the device is operated at a

 

 

 

 

frequency of up to 167 MHz with DDR-I timing.

 

 

 

 

 

TDO

Output

TDO for JTAG.

 

 

 

 

 

TCK

Input

TCK Pin for JTAG.

 

 

 

 

 

TDI

Input

TDI Pin for JTAG.

 

 

 

 

 

TMS

Input

TMS Pin for JTAG.

 

 

 

 

 

NC

N/A

Not Connected to the Die. Is tied to any voltage level.

 

 

 

 

 

NC/72M

N/A

Not Connected to the Die. Is tied to any voltage level.

 

 

 

 

 

NC/144M

N/A

Not Connected to the Die. Is tied to any voltage level.

 

 

 

 

 

NC/288M

N/A

Not Connected to the Die. Is tied to any voltage level.

 

 

 

 

 

VREF

Input

Reference Voltage Input. Static input is used to set the reference level for HSTL inputs, outputs,

 

 

 

Reference

and AC measurement points.

 

 

 

 

 

VDD

Power Supply

Power Supply Inputs to the Core of the Device.

 

VSS

Ground

Ground for the Device.

 

VDDQ

Power Supply

Power Supply Inputs for the Outputs of the Device.

Document Number: 001-06550 Rev. *E

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Contents Selection Guide FeaturesConfigurations Functional DescriptionLogic Block Diagram CY7C1557V18 Logic Block Diagram CY7C1546V18Logic Block Diagram CY7C1550V18 Logic Block Diagram CY7C1548V18CY7C1557V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1546V18 8M xCY7C1550V18 2M x CY7C1548V18 4M xSynchronous Read or Write Input. When Pin DefinitionsPin Name Pin Description BWS BWS2, BWS3TCK Pin for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TDO for JtagFunctional Overview SRAM#1 SRAM#2 Valid Data Indicator QvldApplication Example Echo ClocksComments Write Cycle DescriptionsOperation BWS0 BWS1BWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTCK TAP Controller Block DiagramTAP Electrical Characteristics TDITAP Timing and Test Conditions TAP AC Switching CharacteristicsRegister Name Bit Size Identification Register DefinitionsScan Register Sizes Instruction CodesBit Number Bump ID DLL Constraints Power Up Sequence in DDR-II+ SramPower Up Waveforms Power Up SequenceRange Ambient Electrical CharacteristicsDC Electrical Characteristics Maximum RatingsParameter Description Test Conditions Max Unit AC Electrical CharacteristicsCapacitance Thermal ResistanceAC Test Loads and Waveforms AC Test Loads and WaveformsDLL Timing Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Parameter Min MaxRead NOP Write Switching WaveformsRead/Write/Deselect Sequence 29, 30, 31 NOPOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramDocument History ECN No Issue Orig. Description of Change DateREV
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