Cypress CY7C1546V18 Identification Register Definitions, Scan Register Sizes, Instruction Codes

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CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Identification Register Definitions

	Instruction Field		Value			Description
	Instruction Field	CY7C1546V18	CY7C1557V18	CY7C1548V18	CY7C1550V18	Description
		CY7C1546V18	CY7C1557V18	CY7C1548V18	CY7C1550V18
	Revision Number	000	000	000	000	Version number.
	(31:29)
	Cypress Device ID	11010111100000100	11010111100001100	11010111100010100	11010111100100100	Defines the type of
	(28:12)					SRAM.
	Cypress JEDEC ID	00000110100	00000110100	00000110100	00000110100	Enables unique
	(11:1)					identification of
						SRAM vendor.
	ID Register	1	1	1	1	Indicates the
	Presence (0)					presence of an ID
						register.

Scan Register Sizes

Register Name	Bit Size
Instruction	3

Bypass	1

ID	32

Boundary Scan	109

Instruction Codes

Instruction	Code	Description
EXTEST	000	Captures the input and output ring contents.

IDCODE	001	Loads the ID register with the vendor ID code and places the register between TDI and TDO.
		This operation does not affect SRAM operation.
SAMPLE Z	010	Captures the input and output contents. Places the boundary scan register between TDI and
		TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED	011	Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD	100	Captures the input and output ring contents. Places the boundary scan register between TDI
		and TDO. Does not affect the SRAM operation.
RESERVED	101	Do Not Use: This instruction is reserved for future use.

RESERVED	110	Do Not Use: This instruction is reserved for future use.

BYPASS	111	Places the bypass register between TDI and TDO. This operation does not affect SRAM
		operation.

Document Number: 001-06550 Rev. *E

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Contents Configurations FeaturesFunctional Description Selection GuideLogic Block Diagram CY7C1557V18 Logic Block Diagram CY7C1546V18Logic Block Diagram CY7C1550V18 Logic Block Diagram CY7C1548V18Ball Fbga 15 x 17 x 1.4 mm Pinout Pin ConfigurationCY7C1546V18 8M x CY7C1557V18 8M xCY7C1550V18 2M x CY7C1548V18 4M xPin Name Pin Description Pin DefinitionsBWS BWS2, BWS3 Synchronous Read or Write Input. WhenPower Supply Inputs for the Outputs of the Device Power Supply Inputs to the Core of the DeviceTDO for Jtag TCK Pin for JtagFunctional Overview Application Example Valid Data Indicator QvldEcho Clocks SRAM#1 SRAM#2Operation Write Cycle DescriptionsBWS0 BWS1 CommentsBWS0 BWS1 BWS2 BWS3 BWS0Ieee 1149.1 Serial Boundary Scan Jtag Idcode State diagram for the TAP controller follows TAP Controller State DiagramTAP Electrical Characteristics TAP Controller Block DiagramTDI TCKTAP Timing and Test Conditions TAP AC Switching CharacteristicsScan Register Sizes Identification Register DefinitionsInstruction Codes Register Name Bit SizeBit Number Bump ID Power Up Waveforms Power Up Sequence in DDR-II+ SramPower Up Sequence DLL ConstraintsDC Electrical Characteristics Electrical CharacteristicsMaximum Ratings Range AmbientCapacitance AC Electrical CharacteristicsThermal Resistance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit Switching CharacteristicsParameter Min Max DLL TimingRead/Write/Deselect Sequence 29, 30, 31 Switching WaveformsNOP Read NOP WriteOrdering Information 300 Ball Fbga 15 x 17 x 1.4 mm Package DiagramREV ECN No Issue Orig. Description of Change DateDocument History