CY7C1546V18, CY7C1557V18
CY7C1548V18, CY7C1550V18
Truth Table
The truth table for CY7C1546V18, CY7C1557V18, CY7C1548V18, and CY7C1550V18 follows. [3, 4, 5, 6, 7, 8]
Operation | K |
| LD | R/W | DQ | DQ | ||||||||||
Write Cycle: |
| L | L | D(A) at K(t + 1) ↑ | D(A+1) at |
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K(t + 1) ↑ | ||||||||||||||||
Load address; wait one cycle; |
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input write data on consecutive K and | K | rising edges. |
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Read Cycle: (2.0 cycle Latency) |
| L | H | Q(A) at K(t + 2) ↑ | Q(A+1) at |
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K(t + 2) ↑ | ||||||||||||||||
Load address; wait two cycle; |
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read data on consecutive K and | K | rising edges. |
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NOP: No Operation |
| H | X | High Z | High Z | |||||||||||
Standby: Clock Stopped | Stopped |
| X | X | Previous State | Previous State |
Write Cycle Descriptions
The write cycle description table for CY7C1546V18 and CY7C1548V18 follows. [3, 9]
| BWS0/ | BWS1/ | K |
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| NWS0 |
| NWS1 |
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| L |
| L |
| – | During the data portion of a write sequence: |
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| CY7C1546V18 − both nibbles (D[7:0]) are written into the device. |
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| CY7C1548V18 − both bytes (D[17:0]) are written into the device. |
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| L |
| L | – | During the data portion of a write sequence: |
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| CY7C1546V18 − both nibbles (D[7:0]) are written into the device. |
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| CY7C1548V18 − both bytes (D[17:0]) are written into the device. |
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| L |
| H |
| – | During the data portion of a write sequence: |
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| CY7C1546V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] | remains unaltered. | |
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| CY7C1548V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] | remains unaltered. | |
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| H | – | During the data portion of a write sequence: |
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| CY7C1546V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] | remains unaltered. | |
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| CY7C1548V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] | remains unaltered. | |
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| – | During the data portion of a write sequence: |
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| CY7C1546V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] | remains unaltered. | |
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| CY7C1548V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] | remains unaltered. | |
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| L | – | During the data portion of a write sequence: |
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| CY7C1546V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] | remains unaltered. | |
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| CY7C1548V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] | remains unaltered. | |
| H |
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| – | No data is written into the devices during this portion of a write operation. |
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| H |
| H | – | No data is written into the devices during this portion of a write operation. |
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Notes
3.X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
4.Device powers up deselected with the outputs in a
5.“A” represents address location latched by the devices when transaction was initiated. A + 1 represents the address sequence in the burst.
6.“t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
7.Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.
8.Cypress recommends that K = K = HIGH when clock is stopped. This is not essential but permits most rapid restart by overcoming transmission line charging symmetrically.
9.Is based on a write cycle is initiated as per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 is altered on different portions of a write cycle, as long as the setup and hold requirements are met.
Document Number: | Page 10 of 28 |
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