Cypress CY7C1550V18, CY7C1548V18, CY7C1546V18, CY7C1557V18 manual 300

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CY7C1546V18, CY7C1557V18

CY7C1548V18, CY7C1550V18

Ordering Information (continued)

Not all of the speed, package, and temperature ranges are available. Contact your local sales representative or visit www.cypress.com for actual products offered.

Speed	Ordering Code	Package	Package Type	Operating
(MHz)	Ordering Code	Diagram	Package Type	Range
300	CY7C1546V18-300BZC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Commercial

	CY7C1557V18-300BZC

	CY7C1548V18-300BZC

	CY7C1550V18-300BZC

	CY7C1546V18-300BZXC	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1557V18-300BZXC

	CY7C1548V18-300BZXC

	CY7C1550V18-300BZXC

	CY7C1546V18-300BZI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm)	Industrial

	CY7C1557V18-300BZI

	CY7C1548V18-300BZI

	CY7C1550V18-300BZI

	CY7C1546V18-300BZXI	51-85195	165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

	CY7C1557V18-300BZXI

	CY7C1548V18-300BZXI

	CY7C1550V18-300BZXI

Document Number: 001-06550 Rev. *E

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Contents Functional Description FeaturesConfigurations Selection GuideLogic Block Diagram CY7C1546V18 Logic Block Diagram CY7C1557V18Logic Block Diagram CY7C1548V18 Logic Block Diagram CY7C1550V18CY7C1546V18 8M x Pin ConfigurationBall Fbga 15 x 17 x 1.4 mm Pinout CY7C1557V18 8M xCY7C1548V18 4M x CY7C1550V18 2M xBWS BWS2, BWS3 Pin DefinitionsPin Name Pin Description Synchronous Read or Write Input. WhenTDO for Jtag Power Supply Inputs to the Core of the DevicePower Supply Inputs for the Outputs of the Device TCK Pin for JtagFunctional Overview Echo Clocks Valid Data Indicator QvldApplication Example SRAM#1 SRAM#2BWS0 BWS1 Write Cycle DescriptionsOperation CommentsBWS0 BWS0 BWS1 BWS2 BWS3Ieee 1149.1 Serial Boundary Scan Jtag Idcode TAP Controller State Diagram State diagram for the TAP controller followsTDI TAP Controller Block DiagramTAP Electrical Characteristics TCKTAP AC Switching Characteristics TAP Timing and Test ConditionsInstruction Codes Identification Register DefinitionsScan Register Sizes Register Name Bit SizeBit Number Bump ID Power Up Sequence Power Up Sequence in DDR-II+ SramPower Up Waveforms DLL ConstraintsMaximum Ratings Electrical CharacteristicsDC Electrical Characteristics Range AmbientThermal Resistance AC Electrical CharacteristicsCapacitance Parameter Description Test Conditions Max UnitAC Test Loads and Waveforms AC Test Loads and WaveformsParameter Min Max Switching CharacteristicsCypress Consortium Description 375 MHz 333 MHz 300 MHz Unit DLL TimingNOP Switching WaveformsRead/Write/Deselect Sequence 29, 30, 31 Read NOP WriteOrdering Information 300 Package Diagram Ball Fbga 15 x 17 x 1.4 mmREV ECN No Issue Orig. Description of Change DateDocument History