Cypress CYDC064B08, CYDC064B16, CYDC256B16 manual Features, Selection Guide for VCC =, Unit

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

Features

•True dual-ported memory cells which allow simulta- neous access of the same memory location

•4/8/16k × 16 and 8/16k × 8 organization

•High-speed access: 40 ns

•Ultra Low operating power

—Active: ICC = 15 mA (typical) at 55 ns

—Active: ICC = 25 mA (typical) at 40 ns

—Standby: ISB3 = 2 µA (typical)

•Port-independent 1.8V, 2.5V, and 3.0V I/Os

•Lead (Pb)-free 14 x 14 x 1.4 mm 100-pin TQFP Package

•Full asynchronous operation

•Pin select for Master or Slave

•Expandable data bus to 32 bits with Master/Slave chip select when using more than one device

•On-chip arbitration logic

•On-chip semaphore logic

•Input Read Registers and Output Drive Registers

•INT flag for port-to-port communication

•Separate upper-byte and lower-byte control

•Commercial and industrial temperature ranges

Selection Guide for VCC = 1.8V

 

CYDC256B16, CYDC128B16,

CYDC256B16, CYDC128B16,

 

 

CYDC064B16, CYDC128B08,

CYDC064B16, CYDC128B08,

 

 

CYDC064B08

CYDC064B08

 

 

-40

-55

 

Port I/O Voltages (P1-P2)

1.8V-1.8V

1.8V-1.8V

Unit

 

 

 

 

Maximum Access Time

40

55

ns

 

 

 

 

Typical Operating Current

25

15

mA

 

 

 

 

Typical Standby Current for ISB1

2

2

µA

Typical Standby Current for ISB3

2

2

µA

Selection Guide for VCC = 2.5V

 

CYDC256B16, CYDC128B16,

CYDC256B16, CYDC128B16,

 

 

CYDC064B16, CYDC128B08,

CYDC064B16, CYDC128B08,

 

 

CYDC064B08

CYDC064B08

 

 

-40

-55

 

Port I/O Voltages (P1-P2)

2.5V-2.5V

2.5V-2.5V

Unit

 

 

 

 

Maximum Access Time

40

55

ns

 

 

 

 

Typical Operating Current

39

28

mA

 

 

 

 

Typical Standby Current for ISB1

6

6

µA

Typical Standby Current for ISB3

4

4

µA

Selection Guide for VCC = 3.0V

 

 

CYDC256B16, CYDC128B16,

CYDC256B16, CYDC128B16,

 

 

 

 

CYDC064B16, CYDC128B08,

CYDC064B16, CYDC128B08,

 

 

 

 

 

CYDC064B08

CYDC064B08

 

 

 

 

 

 

-40

-55

 

 

 

Port I/O Voltages (P1-P2)

 

 

3.0V-3.0V

3.0V-3.0V

 

 

Unit

 

 

 

 

 

 

 

 

Maximum Access Time

 

 

40

55

 

 

ns

 

 

 

 

 

 

 

 

Typical Operating Current

 

 

49

42

 

 

mA

 

 

 

 

 

 

 

 

Typical Standby Current for ISB1

 

 

7

7

 

 

µA

Typical Standby Current for ISB3

 

 

6

6

 

 

µA

Cypress Semiconductor Corporation

•

198 Champion Court •

San Jose, CA 95134-1709

•

408-943-2600

Document #: 001-01638 Rev. *E

 

 

Revised January 25, 2007

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Contents Selection Guide for VCC = FeaturesCYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 UnitCYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsBusy InterruptsMaster/Slave Input Read RegisterArchitecture 0 -I/O 5 -I/O Mode 0 -I/O 2 -I/O ModeInput Read Register Operation16 Semaphore Operation Example FunctionRange Ambient Temperature Electrical Characteristics for V CC =Maximum Ratings23 Operating RangeStandb y Cur rent One Port Cmos Ind Input Leakage CurrentODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portInput High Voltage 5V any port Input LOW Voltage 5V any port 0V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsInterrupt Timing Busy TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.1 Either Port Address Access36, 37 Switching WaveformsRead Cycle No.2 Either Port CE/OE Access36, 39 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53CER Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54Right Address Valid First Right Side Clears INT R Interrupt Timing Diagrams Left Side Sets INT RRight Side Sets Intl Left Side Clears INT LOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change
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