Cypress CYDC128B16, CYDC064B16, CYDC064B08, CYDC256B16, CYDC128B08 manual Ordering Information

Page 24

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Ordering Information

16k x16 1.8V Asynchronous Dual-Port SRAM

Speed

Ordering Code

 

Package

Package Type

Operating

(ns)

 

Name

Range

 

 

 

 

 

 

40

CYDC256B16-40AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC256B16-55AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC256B16-55AXI

 

AZ0AB

100-pin Lead-free TQFP

Industrial

 

 

 

 

 

 

8k x16 1.8V Asynchronous Dual-Port SRAM

 

 

 

Speed

Ordering Code

 

Package

Package Type

Operating

(ns)

 

Name

Range

 

 

 

 

 

 

40

CYDC128B16-40AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC128B16-55AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC128B16-55AXI

 

AZ0AB

100-pin Lead-free TQFP

Industrial

 

 

 

 

 

 

4k x16 1.8V Asynchronous Dual-Port SRAM

 

 

 

Speed

Ordering Code

 

Package

Package Type

Operating

(ns)

 

Name

Range

 

 

 

 

 

 

40

CYDC064B16-40AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC064B16-55AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC064B16-55AXI

 

AZ0AB

100-pin Lead-free TQFP

Industrial

 

 

 

 

 

 

16k x8 1.8V Asynchronous Dual-Port SRAM

 

 

 

Speed

Ordering Code

 

Package

Package Type

Operating

(ns)

 

Name

Range

 

 

 

 

 

 

40

CYDC128B08-40AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC128B08-55AXC

 

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

 

55

CYDC128B08-55AXI

 

AZ0AB

100-pin Lead-free TQFP

Industrial

 

 

 

 

 

 

8k x8 1.8V Asynchronous Dual-Port SRAM

 

 

 

Speed

Ordering Code

Package

Package Type

Operating

(ns)

Name

Range

 

 

 

 

 

40

CYDC064B08-40AXC

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

55

CYDC064B08-55AXC

AZ0AB

100-pin Lead-free TQFP

Commercial

 

 

 

 

 

55

CYDC064B08-55AXI

AZ0AB

100-pin Lead-free TQFP

Industrial

 

 

 

 

 

Document #: 001-01638 Rev. *E

Page 24 of 26

[+] Feedback

Image 24
Contents Features Selection Guide for VCC =CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 UnitCYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top ViewPin Configurations 7, 8, 9 CYDC064B08Pin Definitions Functional DescriptionInterrupts BusyMaster/Slave Input Read RegisterArchitecture 0 -I/O 2 -I/O Mode 0 -I/O 5 -I/O ModeInput Read Register Operation16 Semaphore Operation Example FunctionElectrical Characteristics for V CC = Range Ambient TemperatureMaximum Ratings23 Operating RangeInput Leakage Current Standb y Cur rent One Port Cmos IndOutput LOW Voltage I OL = 2 mA 5V any port 0V any port ODR Output LOW Voltage I OL = 8 mA 5V any port 0V any portInput High Voltage 5V any port Input LOW Voltage 5V any port 0V any portCapacitance Parameter Description Test Conditions Max UnitAC7Test Loads and Waveforms Write CycleBusy Timing Interrupt TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Switching Waveforms Read Cycle No.1 Either Port Address Access36, 37Read Cycle No.2 Either Port CE/OE Access36, 39 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOWBusy Timing Diagram No.1 CE Arbitration CEL Valid First54 CER Valid FirstRight Address Valid First Interrupt Timing Diagrams Left Side Sets INT R Right Side Clears INT RRight Side Sets Intl Left Side Clears INT LOrdering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100Issue Date Orig. Description of Change Document History