Cypress CYDC128B08, CYDC064B16, CYDC064B08, CYDC256B16 AC7Test Loads and Waveforms, Write Cycle

Page 13

CYDC256B16, CYDC128B16, CYDC064B16, CYDC128B08, CYDC064B08

AC7Test Loads and Waveforms

 

 

 

 

 

 

 

 

 

3.0V/2.5V/1.8V

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

 

 

R1

OUTPUT

 

 

 

 

 

RTH = 6 kΩ

 

 

 

 

 

 

 

 

 

 

 

 

 

C = 30 pF

 

 

 

 

 

 

 

C = 30 pF

 

 

 

 

 

 

 

 

 

 

 

 

R2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

C = 5 pF

VTH = 0.8V

3.0V/2.5V/1.8V

R1

R2

(a) Normal Load (Load 1)

 

 

(b) Thévenin Equivalent (Load 1)

(c) Three-State Delay (Load 2)

 

 

 

 

 

 

 

 

ALL INPUT PULSES

 

 

(Used for tLZ, tHZ, tHZWE, and tLZWE

 

3.0V/2.5V

1.8V

1.8V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

including scope and jig)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R1

1022Ω

13500Ω

 

 

 

 

 

 

 

 

 

 

 

 

90%

 

 

 

 

 

10%

 

 

 

 

 

 

90%

 

 

 

 

10%

 

R2

792Ω

10800Ω

GND

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

≤ 3 ns

 

 

 

 

 

≤ 3 ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Characteristics for V = 1.8V Over the Operating Range[27]

 

 

 

 

 

 

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

CYDC256B16,

CYDC256B16,

 

 

 

 

 

 

CYDC128B16,

CYDC128B16,

 

 

 

 

 

 

CYDC064B16,

CYDC064B16,

 

 

 

 

 

 

CYDC128B08,

CYDC128B08,

 

 

 

 

 

 

CYDC064B08

CYDC064B08

 

 

 

 

 

 

 

-40

 

-55

 

Parameter

 

 

 

Description

Min.

 

Max.

Min.

 

Max.

Unit

Read Cycle

 

 

 

 

 

 

 

 

 

 

tRC

 

Read Cycle Time

40

 

 

55

 

 

ns

tAA

 

Address to Data Valid

 

 

40

 

 

55

ns

tOHA

 

Output Hold From Address Change

5

 

 

5

 

 

ns

tACE[28]

 

 

 

LOW to Data Valid

 

 

40

 

 

55

ns

CE

 

 

tDOE

 

 

 

LOW to Data Valid

 

 

25

 

 

30

ns

OE

 

 

tLZOE[29, 30, 31]

 

 

 

Low to Low Z

5

 

 

5

 

 

ns

OE

 

 

 

 

tHZOE[29, 30, 31]

 

 

 

HIGH to High Z

 

 

15

 

 

25

ns

OE

 

 

tLZCE[29, 30, 31]

 

 

LOW to Low Z

5

 

 

5

 

 

ns

CE

 

 

 

 

tHZCE[29, 30, 31]

 

 

HIGH to High Z

 

 

15

 

 

25

ns

CE

 

 

tPU[31]

 

 

LOW to Power-Up

0

 

 

0

 

 

ns

CE

 

 

 

 

tPD[31]

 

 

HIGH to Power-Down

 

 

40

 

 

55

ns

CE

 

 

tABE[28]

 

Byte Enable Access Time

 

 

40

 

 

55

ns

Write Cycle

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tWC

 

Write Cycle Time

40

 

 

55

 

 

ns

tSCE[28]

 

 

LOW to Write End

30

 

 

45

 

 

ns

CE

 

 

 

 

tAW

 

Address Valid to Write End

30

 

 

45

 

 

ns

Notes:

27.Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC, and output loading of the specified IOI/IOH and 30-pF load capacitance.

28.To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.

29.At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.

30.Test conditions used are Load 3.

31.This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform

Document #: 001-01638 Rev. *E

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Contents Selection Guide for VCC = FeaturesCYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 UnitCYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsBusy InterruptsMaster/Slave Input Read RegisterArchitecture 0 -I/O 5 -I/O Mode 0 -I/O 2 -I/O ModeInput Read Register Operation16 Semaphore Operation Example FunctionRange Ambient Temperature Electrical Characteristics for V CC =Maximum Ratings23 Operating RangeStandb y Cur rent One Port Cmos Ind Input Leakage CurrentODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portInput High Voltage 5V any port Input LOW Voltage 5V any port 0V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsInterrupt Timing Busy TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.1 Either Port Address Access36, 37 Switching WaveformsRead Cycle No.2 Either Port CE/OE Access36, 39 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53CER Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54Right Address Valid First Right Side Clears INT R Interrupt Timing Diagrams Left Side Sets INT RRight Side Sets Intl Left Side Clears INT LOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change
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