Cypress CYDC064B08, CYDC064B16, CYDC256B16 Output LOW Voltage I OL = 2 mA 5V any port 0V any port

Page 11

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Electrical Characteristics for VCC = 2.5V Over the Operating Range

 

 

 

 

 

CYDC256B16,

CYDC256B16,

 

 

 

 

 

 

CYDC128B16,

CYDC128B16,

 

 

 

 

 

 

CYDC064B16,

CYDC064B16,

 

 

 

 

 

 

CYDC128B08,

CYDC128B08,

 

 

 

 

 

 

CYDC064B08

CYDC064B08

 

 

 

 

 

 

-40

 

-55

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Description

 

P1 I/O

P2 I/O

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

 

Voltage

Voltage

VOH

Output HIGH Voltage (IOH = –2 mA)

2.5V (any port)

2.0

 

 

2.0

 

 

V

 

Output HIGH Voltage (IOH = –2 mA)

3.0V (any port)

2.1

 

 

2.1

 

 

V

VOL

Output LOW Voltage (IOL = 2 mA)

 

2.5V (any port)

 

 

0.4

 

 

0.4

V

 

Output LOW Voltage (IOL = 2 mA)

 

3.0V (any port)

 

 

0.4

 

 

0.4

V

VOL ODR

ODR Output LOW Voltage (IOL = 8 mA)

2.5V (any port)

 

 

0.2

 

 

0.2

V

 

 

 

3.0V (any port)

 

 

0.2

 

 

0.2

V

 

 

 

 

 

 

 

 

 

 

 

VIH

Input HIGH Voltage

 

2.5V (any port)

1.7

 

VDDIO

1.7

 

VDDIO

V

 

 

 

 

 

 

 

+ 0.3

 

 

+ 0.3

 

 

 

 

3.0V (any port)

2.0

 

VDDIO

2.0

 

VDDIO

V

 

 

 

 

 

 

 

+ 0.2

 

 

+ 0.2

 

VIL

Input LOW Voltage

 

2.5V (any port)

–0.3

 

0.6

–0.3

 

0.6

V

 

 

 

3.0V (any port)

–0.2

 

0.7

–0.2

 

0.7

V

 

 

 

 

 

 

 

 

 

 

 

 

IOZ

Output Leakage Current

 

2.5V

2.5V

–1

 

1

–1

 

1

µA

 

 

 

3.0V

3.0V

–1

 

1

–1

 

1

µA

 

 

 

 

 

 

 

 

 

 

 

 

ICEX ODR

ODR Output Leakage Current.

 

2.5V

2.5V

–1

 

1

–1

 

1

µA

 

VOUT = VCC

 

 

 

 

 

 

 

 

 

 

 

 

3.0V

3.0V

–1

 

1

–1

 

1

µA

IIX

Input Leakage Current

 

2.5V

2.5V

–1

 

1

–1

 

1

µA

 

 

 

3.0V

3.0V

–1

 

1

–1

 

1

µA

 

 

 

 

 

 

 

 

 

 

 

 

ICC

Operating Current (VCC = Max.,

Ind.

2.5V

2.5V

 

39

55

 

28

40

mA

 

IOUT = 0 mA) Outputs Disabled

 

 

 

 

 

 

 

 

 

 

ISB1

Standby Current (Both Ports TTL

Ind.

2.5V

2.5V

 

6

8

 

6

8

µA

 

Level) CEL and CER ≥ VCC – 0.2,

 

 

 

 

 

 

 

 

 

 

 

SEM L= SEMR = VCC – 0.2, f=fMAX

 

 

 

 

 

 

 

 

 

 

ISB2

Standby Current (One Port TTL

Ind.

2.5V

2.5V

 

21

30

 

18

25

mA

 

Level) CEL CER ≥ VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

ISB3

Standby Current (Both Ports

Ind.

2.5V

2.5V

 

4

6

 

4

6

µA

 

CMOS Level) CEL & CER

 

 

 

 

 

 

 

 

 

 

 

VCC − 0.2V, SEML and SEMR >

 

 

 

 

 

 

 

 

 

 

 

VCC – 0.2V, f = 0

 

 

 

 

 

 

 

 

 

 

ISB4

Standby Current (One Port CMOS

Ind.

2.5V

2.5V

 

21

30

 

18

25

mA

 

Level) CEL CER ≥ VIH, f = fMAX[25]

 

 

 

 

 

 

 

 

 

 

Document #: 001-01638 Rev. *E

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Image 11
Contents Unit FeaturesSelection Guide for VCC = CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08CYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsInput Read Register InterruptsBusy Master/SlaveArchitecture Semaphore Operation Example Function 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Input Read Register Operation16Operating Range Electrical Characteristics for V CC =Range Ambient Temperature Maximum Ratings23Standb y Cur rent One Port Cmos Ind Input Leakage CurrentInput LOW Voltage 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input High Voltage 5V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsSemaphore Timing Busy TimingInterrupt Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No Either Port36, 38, 41 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No.2 Either Port CE/OE Access36, 39Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53Right Address Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54CER Valid First Left Side Clears INT L Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Right Side Sets IntlOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change