Cypress CYDC128B08 manual Interrupt Timing Diagrams Left Side Sets INT R, Right Side Clears INT R

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Waveforms (continued)

Interrupt Timing Diagrams

Left Side Sets INTR:	tWC
ADDRESSL	WRITE 1FFF (OR 1/3FFF)
CEL	tHA[55]
CEL
R/WL
INTR
	tINS [56]

Right Side Clears INTR:

tRC

ADDRESSR

READ 1FFF

(OR 1/3FFF)

CER

tINR[56]

R/WR

OER

INTR

Right Side Sets INTL:

ADDRESSR

CER

R/WR

INTL

tWC

WRITE 1FFE (OR 1/3FFE)

tHA[55]

tINS[56]

Left Side Clears INTL:	tRC
ADDRESSR	READ 1FFE
ADDRESSR	OR 1/3FFE)
CEL
	tINR[56]
R/WL
OEL
INTL

Notes:

55.tHA depends on which enable pin (CEL or R/WL) is deasserted first.

56.tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.

Document #: 001-01638 Rev. *E

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Contents Unit FeaturesSelection Guide for VCC = CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08CYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsInput Read Register InterruptsBusy Master/SlaveArchitecture Semaphore Operation Example Function 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Input Read Register Operation16Operating Range Electrical Characteristics for V CC =Range Ambient Temperature Maximum Ratings23Standb y Cur rent One Port Cmos Ind Input Leakage CurrentInput LOW Voltage 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input High Voltage 5V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsSemaphore Timing Busy TimingInterrupt Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No Either Port36, 38, 41 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No.2 Either Port CE/OE Access36, 39Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53Right Address Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54CER Valid First Left Side Clears INT L Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Right Side Sets IntlOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change