Cypress CYDC256B16 High after Busy Slave, SEM Address Access Time Document # 001-01638 Rev. *E

Page 17

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Characteristics for VCC = 3.0V Over the Operating Range (continued)

CYDC256B16,

CYDC256B16,

CYDC128B16,

CYDC128B16,

CYDC064B16,

CYDC064B16,

CYDC128B08,

CYDC128B08,

Unit

CYDC064B08

CYDC064B08

-40

-55

Parameter

Description

Min.

Max.

Min.

Max.

tHZWE[30, 31]

R/W

LOW to High Z

15

25

ns

tLZWE[30, 31]

HIGH to Low Z

0

0

ns

R/W

tWDD[32]

Write Pulse to Data Delay

55

80

ns

tDDD[32]

Write Data Valid to Read Data Valid

55

80

ns

Busy Timing[33]

tBLA

BUSY

LOW from Address Match

30

45

ns

tBHA

HIGH from Address Mismatch

30

45

ns

BUSY

tBLC

LOW from

LOW

30

45

ns

BUSY

CE

tBHC

HIGH from

HIGH

30

45

ns

BUSY

CE

tPS[34]

Port Set-up for Priority

5

5

ns

tWB

R/W

HIGH after BUSY (Slave)

0

0

ns

tWH

HIGH after

HIGH (Slave)

20

35

ns

R/W

BUSY

tBDD[35]

HIGH to Data Valid

30

40

ns

BUSY

Interrupt Timing[33]

tINS

INT

Set Time

35

45

ns

tINR

Reset Time

35

45

ns

INT

Semaphore Timing

tSOP

SEM Flag Update Pulse

(OE

or

SEM)

10

15

ns

tSWRD

SEM Flag Write to Read Time

10

10

ns

tSPS

SEM Flag Contention Window

10

10

ns

tSAA

SEM Address Access Time

40

55

ns

Document #: 001-01638 Rev. *E

Page 17 of 26

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Contents Selection Guide for VCC = FeaturesCYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 UnitCYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsBusy InterruptsMaster/Slave Input Read RegisterArchitecture 0 -I/O 5 -I/O Mode 0 -I/O 2 -I/O ModeInput Read Register Operation16 Semaphore Operation Example FunctionRange Ambient Temperature Electrical Characteristics for V CC =Maximum Ratings23 Operating RangeStandb y Cur rent One Port Cmos Ind Input Leakage CurrentODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portInput High Voltage 5V any port Input LOW Voltage 5V any port 0V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsSemaphore Timing Busy TimingInterrupt Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.1 Either Port Address Access36, 37 Switching WaveformsRead Cycle No.2 Either Port CE/OE Access36, 39 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53Right Address Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54CER Valid First Right Side Clears INT R Interrupt Timing Diagrams Left Side Sets INT RRight Side Sets Intl Left Side Clears INT LOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change