Cypress CYDC064B16, CYDC064B08, CYDC256B16, CYDC128B08, CYDC128B16 manual High after Slave

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Characteristics for VCC = 2.5V Over the Operating Range

CYDC256B16,

CYDC256B16,

CYDC128B16,

CYDC128B16,

CYDC064B16,

CYDC064B16,

CYDC128B08,

CYDC128B08,

CYDC064B08

CYDC064B08

-40

-55

Parameter

Description

Unit

Min.

Max.

Min.

Max.

Read Cycle

tRC

Read Cycle Time

40

55

ns

tAA

Address to Data Valid

40

55

ns

tOHA

Output Hold From Address Change

5

5

ns

tACE[28]

LOW to Data Valid

40

55

ns

CE

tDOE

LOW to Data Valid

25

30

ns

OE

tLZOE[29, 30, 31]

Low to Low Z

2

2

ns

OE

tHZOE[29, 30, 31]

HIGH to High Z

15

15

ns

OE

tLZCE[29, 30, 31]

LOW to Low Z

2

2

ns

CE

tHZCE[29, 30, 31]

HIGH to High Z

15

15

ns

CE

tPU[31]

LOW to Power-Up

0

0

ns

CE

tPD[31]

HIGH to Power-Down

40

55

ns

CE

tABE[28]

Byte Enable Access Time

40

55

ns

Write Cycle

tWC

Write Cycle Time

40

55

ns

tSCE[28]

LOW to Write End

30

45

ns

CE

tAW

Address Valid to Write End

30

45

ns

tHA

Address Hold From Write End

0

0

ns

tSA[28]

Address Set-up to Write Start

0

0

ns

tPWE

Write Pulse Width

25

40

ns

tSD

Data Set-up to Write End

20

30

ns

tHD

Data Hold From Write End

0

0

ns

tHZWE[30, 31]

LOW to High Z

15

25

ns

R/W

tLZWE[30, 31]

HIGH to Low Z

0

0

ns

R/W

tWDD[32]

Write Pulse to Data Delay

55

80

ns

tDDD[32]

Write Data Valid to Read Data Valid

55

80

ns

Busy Timing[33]

tBLA

BUSY

LOW from Address Match

30

45

ns

tBHA

HIGH from Address Mismatch

30

45

ns

BUSY

tBLC

LOW from

LOW

30

45

ns

BUSY

CE

tBHC

HIGH from

HIGH

30

45

ns

BUSY

CE

tPS[34]

Port Set-up for Priority

5

5

ns

tWB

HIGH after

(Slave)

0

0

ns

R/W

BUSY

tWH

HIGH after

HIGH (Slave)

20

35

ns

R/W

BUSY

tBDD[35]

HIGH to Data Valid

30

40

ns

BUSY

Document #: 001-01638 Rev. *E

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Contents Unit FeaturesSelection Guide for VCC = CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08CYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsInput Read Register InterruptsBusy Master/SlaveArchitecture Semaphore Operation Example Function 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Input Read Register Operation16Operating Range Electrical Characteristics for V CC =Range Ambient Temperature Maximum Ratings23Standb y Cur rent One Port Cmos Ind Input Leakage CurrentInput LOW Voltage 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input High Voltage 5V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsBusy Timing Interrupt TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No Either Port36, 38, 41 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No.2 Either Port CE/OE Access36, 39Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53Busy Timing Diagram No.1 CE Arbitration CEL Valid First54 CER Valid FirstRight Address Valid First Left Side Clears INT L Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Right Side Sets IntlOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change