Cypress CYDC064B08, CYDC064B16 manual Document History, Issue Date Orig. Description of Change

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Document History Page

Document Title: CYDC256B16/CYDC128B16/CYDC064B16/CYDC128B08/CYDC064B08 1.8V 4k/8k/16k x 16 and 8k/16k x 8 ConsuMoBL Dual-Port Static RAM

Document Number: 001-01638

REV.	ECN NO.	Issue Date	Orig. of	Description of Change
REV.	ECN NO.	Issue Date	Change	Description of Change

**	385185	SEE ECN	YDT	New data sheet

*A	396697	SEE ECN	KGH	Updated ISB2 and ISB4 typo to mA.
				Updated tINS and tINR for -55 to 31ns.
*B	404777	SEE ECN	KGH	Updated IOH and IOL values for the 1.8V, 2.5V and 3.0V parameters VOH and
				VOL
				Replaced -35 speed bin with -40
				Updated Switching Characteristics for VCC = 2.5V and VCC = 3.0V
				Included note 34
*C	463014	SEE ECN	HKH	Changed spec title to from “Consumer Dual-Port” to “ConsuMoBL Dual-Port”
				Cypress Internet Release
*D	505803	SEE ECN	HKH	Corrected typo in Features and Ordering Info sections.
				Cypress external web release.
*E	735537	SEE ECN	HKH	Corrected typo in Pg5 power supply section
				Updated tDDD timing value to be consistent with tWDD

Document #: 001-01638 Rev. *E

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Contents CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 FeaturesSelection Guide for VCC = UnitCYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top ViewPin Configurations 7, 8, 9 CYDC064B08Pin Definitions Functional DescriptionMaster/Slave InterruptsBusy Input Read RegisterArchitecture Input Read Register Operation16 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Semaphore Operation Example FunctionMaximum Ratings23 Electrical Characteristics for V CC =Range Ambient Temperature Operating RangeInput Leakage Current Standb y Cur rent One Port Cmos IndInput High Voltage 5V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input LOW Voltage 5V any port 0V any portCapacitance Parameter Description Test Conditions Max UnitAC7Test Loads and Waveforms Write CycleSemaphore Timing Busy TimingInterrupt Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.2 Either Port CE/OE Access36, 39 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOWRight Address Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54CER Valid First Right Side Sets Intl Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Left Side Clears INT LOrdering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100Issue Date Orig. Description of Change Document History