Cypress CYDC128B16, CYDC064B16, CYDC064B08 manual Busy Timing, Interrupt Timing, Semaphore Timing

Page 14

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Characteristics for V = 1.8V Over the Operating Range[27] (continued)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYDC256B16,

 

CYDC256B16,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYDC128B16,

 

CYDC128B16,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYDC064B16,

 

CYDC064B16,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYDC128B08,

 

CYDC128B08,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYDC064B08

 

CYDC064B08

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-40

 

 

-55

 

Parameter

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

Unit

 

 

 

 

 

 

 

 

Min.

 

Max.

 

Min.

 

Max.

 

 

 

 

 

 

 

 

 

 

 

tHA

 

Address Hold From Write End

0

 

 

 

0

 

 

ns

tSA[28]

 

Address Set-up to Write Start

0

 

 

 

0

 

 

ns

tPWE

 

Write Pulse Width

25

 

 

 

40

 

 

ns

tSD

 

Data Set-up to Write End

20

 

 

 

30

 

 

ns

tHD

 

Data Hold From Write End

0

 

 

 

0

 

 

ns

tHZWE[30, 31]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

LOW to High Z

 

 

15

 

 

 

25

ns

tLZWE[30, 31]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

HIGH to Low Z

0

 

 

 

0

 

 

ns

tWDD[32]

 

Write Pulse to Data Delay

 

 

55

 

 

 

80

ns

tDDD[32]

 

Write Data Valid to Read Data Valid

 

 

55

 

 

 

80

ns

Busy Timing[33]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tBLA

 

BUSY

 

LOW from Address Match

 

 

30

 

 

 

45

ns

tBHA

 

 

 

 

 

 

 

 

HIGH from Address Mismatch

 

 

30

 

 

 

45

ns

BUSY

 

 

tBLC

 

 

 

 

 

 

 

 

LOW from

 

 

 

LOW

 

 

30

 

 

 

45

ns

BUSY

CE

 

 

tBHC

 

 

 

 

 

 

 

 

HIGH from

 

 

HIGH

 

 

30

 

 

 

45

ns

BUSY

CE

 

 

tPS[34]

 

Port Set-up for Priority

5

 

 

 

5

 

 

ns

tWB

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/W

HIGH after BUSY (Slave)

0

 

 

 

0

 

 

ns

tWH

 

 

 

 

 

 

HIGH after

 

 

 

 

 

HIGH (Slave)

20

 

 

 

35

 

 

ns

R/W

BUSY

 

 

 

 

 

tBDD[35]

 

 

 

 

 

 

 

HIGH to Data Valid

 

 

30

 

 

 

40

ns

BUSY

 

 

Interrupt Timing[33]

 

 

 

 

 

 

 

 

tINS

 

INT

 

Set Time

 

 

35

 

 

 

45

ns

tINR

 

 

 

 

Reset Time

 

 

35

 

 

 

45

ns

INT

 

 

Semaphore Timing

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSOP

 

SEM Flag Update Pulse

(OE

or

SEM)

 

10

 

 

 

15

 

 

ns

tSWRD

 

SEM Flag Write to Read Time

10

 

 

 

10

 

 

ns

tSPS

 

SEM Flag Contention Window

10

 

 

 

10

 

 

ns

tSAA

 

SEM Address Access Time

 

 

40

 

 

 

55

ns

Notes:

32.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.

33.Test conditions used are Load 2.

34.Add 2ns to this value when the I/O ports are operating at different voltages.

35.tBDD is a calculated parameter and is the greater of tWDD–tPWE(actual) or tDDD–tSD(actual).

Document #: 001-01638 Rev. *E

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Contents CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 FeaturesSelection Guide for VCC = UnitCYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top ViewPin Configurations 7, 8, 9 CYDC064B08Pin Definitions Functional DescriptionMaster/Slave InterruptsBusy Input Read RegisterArchitecture Input Read Register Operation16 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Semaphore Operation Example FunctionMaximum Ratings23 Electrical Characteristics for V CC =Range Ambient Temperature Operating RangeInput Leakage Current Standb y Cur rent One Port Cmos IndInput High Voltage 5V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input LOW Voltage 5V any port 0V any portCapacitance Parameter Description Test Conditions Max UnitAC7Test Loads and Waveforms Write CycleSemaphore Timing Busy TimingInterrupt Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.2 Either Port CE/OE Access36, 39 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOWRight Address Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54CER Valid First Right Side Sets Intl Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Left Side Clears INT LOrdering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100Issue Date Orig. Description of Change Document History
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