Cypress CYDC256B16, CYDC064B16 manual Capacitance, Parameter Description Test Conditions Max Unit

Page 12

CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Electrical Characteristics for 3.0V Over the Operating Range

 

 

 

 

 

 

 

 

CYDC256B16,

CYDC256B16,

 

 

 

 

 

 

 

 

 

CYDC128B16,

CYDC128B16,

 

 

 

 

 

 

 

 

 

CYDC064B16,

CYDC064B16,

 

 

 

 

 

 

 

 

 

CYDC128B08,

CYDC128B08,

 

 

 

 

 

 

 

 

 

CYDC064B08

CYDC064B08

 

 

 

 

 

 

 

 

 

-40

 

 

-55

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

Description

 

P1 I/O

P2 I/O

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

 

Voltage

Voltage

VOH

Output HIGH Voltage (IOH = –2 mA)

3.0V (any port)

2.1

 

 

 

2.1

 

 

 

V

VOL

Output LOW Voltage (IOL = 2 mA)

 

3.0V (any port)

 

 

0.4

 

 

 

0.4

V

VOL ODR

ODR Output LOW Voltage (IOL = 8 mA)

3.0V (any port)

 

 

0.2

 

 

 

0.2

V

VIH

Input HIGH Voltage

 

3.0V (any port)

2.0

 

VDDIO

2.0

 

 

VDDIO

V

 

 

 

 

 

 

 

 

 

 

+ 0.2

 

 

 

+ 0.2

 

VIL

Input LOW Voltage

 

 

3.0V (any port)

–0.2

 

0.7

–0.2

 

 

0.7

V

IOZ

Output Leakage Current

 

3.0V

3.0V

–1

 

1

–1

 

 

1

µA

ICEX ODR

ODR Output Leakage Current.

 

3.0V

3.0V

–1

 

1

–1

 

 

1

µA

 

VOUT = VCC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IIX

Input Leakage Current

 

3.0V

3.0V

–1

 

1

–1

 

 

1

µA

ICC

Operating Current (VCC = Max.,

Ind.

3.0V

3.0V

 

49

70

 

42

60

mA

 

IOUT = 0 mA) Outputs Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB1

Standby Current (Both Ports TTL

Ind.

3.0V

3.0V

 

7

10

 

7

10

µA

 

Level) CEL and CER ≥ VCC – 0.2,

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SEML = SEMR = VCC – 0.2, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB2

Standby Current (One Port TTL

Ind.

3.0V

3.0V

 

28

40

 

25

35

mA

 

Level) CEL CER ≥ VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB3

Standby Current (Both Ports

Ind.

3.0V

3.0V

 

6

8

 

6

8

µA

 

CMOS Level) CEL

& CER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC − 0.2V, SEML and SEMR >

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VCC – 0.2V, f = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB4

Standby Current (One Port CMOS

Ind.

3.0V

3.0V

 

28

40

 

25

35

mA

 

Level) CEL CER ≥ VIH, f = fMAX[25]

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitance[26]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Parameter

 

Description

 

 

Test Conditions

 

 

Max.

 

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CIN

 

Input Capacitance

 

 

TA = 25°C, f = 1 MHz,

 

 

9

 

 

pF

 

 

 

 

 

 

VCC = 3.0V

 

 

 

 

 

 

 

 

 

COUT

 

Output Capacitance

 

 

 

 

 

 

10

 

 

pF

 

Note:

26. Tested initially and after any design or process changes that may affect these parameters.

Document #: 001-01638 Rev. *E

Page 12 of 26

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Contents Features Selection Guide for VCC =CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 UnitCYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top ViewPin Configurations 7, 8, 9 CYDC064B08Pin Definitions Functional DescriptionInterrupts BusyMaster/Slave Input Read RegisterArchitecture 0 -I/O 2 -I/O Mode 0 -I/O 5 -I/O ModeInput Read Register Operation16 Semaphore Operation Example FunctionElectrical Characteristics for V CC = Range Ambient TemperatureMaximum Ratings23 Operating RangeInput Leakage Current Standb y Cur rent One Port Cmos IndOutput LOW Voltage I OL = 2 mA 5V any port 0V any port ODR Output LOW Voltage I OL = 8 mA 5V any port 0V any portInput High Voltage 5V any port Input LOW Voltage 5V any port 0V any portCapacitance Parameter Description Test Conditions Max UnitAC7Test Loads and Waveforms Write CycleBusy Timing Interrupt TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Switching Waveforms Read Cycle No.1 Either Port Address Access36, 37Read Cycle No.2 Either Port CE/OE Access36, 39 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOWBusy Timing Diagram No.1 CE Arbitration CEL Valid First54 CER Valid FirstRight Address Valid First Interrupt Timing Diagrams Left Side Sets INT R Right Side Clears INT RRight Side Sets Intl Left Side Clears INT LOrdering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100Issue Date Orig. Description of Change Document History