Cypress CYDC064B16, CYDC064B08 manual Input Leakage Current, Standb y Cur rent One Port Cmos Ind

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Electrical Characteristics for VCC = 1.8V (continued) Over the Operating Range

					CYDC256B16,			CYDC256B16,
					CYDC128B16,			CYDC128B16,
					CYDC064B16,			CYDC064B16,
					CYDC128B08,			CYDC128B08,
					CYDC064B08			CYDC064B08
					-40			-55

Parameter	Description		P1 I/O	P2 I/O	Min.	Typ.	Max.	Min.	Typ.	Max.	Unit
Parameter	Description		Voltage	Voltage	Min.	Typ.	Max.	Min.	Typ.	Max.	Unit
IIX	Input Leakage Current		1.8V	1.8V	–1		1	–1		1	µA
			2.5V	2.5V	–1		1	–1		1	µA

			3.0V	3.0V	–1		1	–1		1	µA

ICC	Operating Current (VCC = Max.,	Ind.	1.8V	1.8V		25	40		15	25	mA
	IOUT = 0 mA) Outputs Disabled
ISB1	Standby Current (Both Ports TTL	Ind.	1.8V	1.8V		2	6		2	6	µA
	Level) CEL and CER ≥ VCC – 0.2,
	SEML = SEMR = VCC – 0.2, f = fMAX
ISB2	Standby Current (One Port TTL	Ind.	1.8V	1.8V		8.5	18		8.5	14	mA
	Level) CEL CER ≥ VIH, f = fMAX
ISB3	Standby Current (Both Ports	Ind.	1.8V	1.8V		2	6		2	6	µA
	CMOS Level) CEL & CER ≥
	VCC − 0.2V, SEML and SEMR >
	VCC – 0.2V, f = 0
ISB4	Standby Current (One Port CMOS	Ind.	1.8V	1.8V		8.5	18		8.5	14	mA
	Level) CEL CER ≥ VIH, f = fMAX[25]

Notes:

25.fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3.

Document #: 001-01638 Rev. *E

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Contents CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 FeaturesSelection Guide for VCC = UnitCYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top ViewPin Configurations 7, 8, 9 CYDC064B08Pin Definitions Functional DescriptionMaster/Slave InterruptsBusy Input Read RegisterArchitecture Input Read Register Operation16 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Semaphore Operation Example FunctionMaximum Ratings23 Electrical Characteristics for V CC =Range Ambient Temperature Operating RangeInput Leakage Current Standb y Cur rent One Port Cmos IndInput High Voltage 5V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input LOW Voltage 5V any port 0V any portCapacitance Parameter Description Test Conditions Max UnitAC7Test Loads and Waveforms Write CycleInterrupt Timing Busy TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.2 Either Port CE/OE Access36, 39 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOWCER Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54Right Address Valid First Right Side Sets Intl Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Left Side Clears INT LOrdering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100Issue Date Orig. Description of Change Document History