Cypress CYDC128B16, CYDC064B16, CYDC064B08 manual Write Cycle No CE Controlled Timing 41, 42, 43

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Waveforms (continued)

Write Cycle No.1: R/W Controlled Timing[41, 42, 43, 44, 45, 46]
		tWC
ADDRESS
			tHZOE[47]
OE
CE [45, 46]		tAW
CE [45, 46]
	tSA	tPWE[44]	tHA
R/W
		tHZWE[47]	tLZWE
DATA OUT	NOTE 48		NOTE 48
		tSD	tHD
DATA IN

Write Cycle No. 2: CE Controlled Timing[41, 42, 43, 48]
tWC
ADDRESS
tAW
CE [45, 46]
tSA	tSCE	tHA
R/W
	tSD	tHD
DATA IN

Notes:

43.tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.

44.If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE.

45.To access RAM, CE = VIL, SEM = VIH.

46.To access upper byte, CE = VIL, UB = VIL, SEM = VIH. To access lower byte, CE = VIL, LB = VIL, SEM = VIH.

47.Transition is measured ±0 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.

48.During this period, the I/O pins are in the output state, and input signals must not be applied.

Document #: 001-01638 Rev. *E

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Contents Unit FeaturesSelection Guide for VCC = CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08CYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsInput Read Register InterruptsBusy Master/SlaveArchitecture Semaphore Operation Example Function 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Input Read Register Operation16Operating Range Electrical Characteristics for V CC =Range Ambient Temperature Maximum Ratings23Standb y Cur rent One Port Cmos Ind Input Leakage CurrentInput LOW Voltage 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input High Voltage 5V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsInterrupt Timing Busy TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No Either Port36, 38, 41 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No.2 Either Port CE/OE Access36, 39Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53CER Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54Right Address Valid First Left Side Clears INT L Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Right Side Sets IntlOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change