Cypress CYDC256B16 Busy Timing Diagram No.1 CE Arbitration CEL Valid First54, CER Valid First

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Waveforms (continued)

Busy Timing Diagram No.1 (CE Arbitration)

CEL Valid First[54]

ADDRESSL,R

CEL

CER

BUSYR

ADDRESS MATCH

tPS

tBLC

tBHC

CER Valid First

ADDRESSL,R

ADDRESS MATCH

CER

CEL

BUSYL

tPS

tBLC

tBHC

Busy Timing Diagram No.2 (Address Arbitration)[54]

Left Address Valid First

tRC or tWC

ADDRESSL

ADDRESS MATCH

ADDRESS MISMATCH

tPS

ADDRESSR

tBLA

tBHA

BUSY

R

Right Address Valid First

ADDRESSR

ADDRESSL

BUSYL

tRC or tWC

ADDRESS MATCH		ADDRESS MISMATCH

tPS

tBLA

tBHA

Note:

54. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.

Document #: 001-01638 Rev. *E

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Contents CYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 FeaturesSelection Guide for VCC = UnitCYDC256B16, CYDC128B16 Pin Configurations 3, 4, 5, 6 Pin Tqfp Top ViewPin Configurations 7, 8, 9 CYDC064B08Pin Definitions Functional DescriptionMaster/Slave InterruptsBusy Input Read RegisterArchitecture Input Read Register Operation16 0 -I/O 2 -I/O Mode0 -I/O 5 -I/O Mode Semaphore Operation Example FunctionMaximum Ratings23 Electrical Characteristics for V CC =Range Ambient Temperature Operating RangeInput Leakage Current Standb y Cur rent One Port Cmos IndInput High Voltage 5V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Input LOW Voltage 5V any port 0V any portCapacitance Parameter Description Test Conditions Max UnitAC7Test Loads and Waveforms Write CycleInterrupt Timing Busy TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.2 Either Port CE/OE Access36, 39 Switching WaveformsRead Cycle No.1 Either Port Address Access36, 37 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Timing Diagram of Semaphore Contention51 Semaphore Read After Write Timing, Either Side49Timing Diagram of Read with Busy M/S=HIGH53 Write Timing with Busy Input M/S = LOWCER Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54Right Address Valid First Right Side Sets Intl Interrupt Timing Diagrams Left Side Sets INT RRight Side Clears INT R Left Side Clears INT LOrdering Information Package Diagram Pin Thin Plastic Quad Flat Pack Tqfp A100Issue Date Orig. Description of Change Document History