Cypress CYDC064B16, CYDC064B08 manual Package Diagram, Pin Thin Plastic Quad Flat Pack Tqfp A100

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Package Diagram

100-Pin Thin Plastic Quad Flat Pack (TQFP) A100

51-85048-*C

All products and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 001-01638 Rev. *E

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© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Contents Selection Guide for VCC = FeaturesCYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 UnitCYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsBusy InterruptsMaster/Slave Input Read RegisterArchitecture 0 -I/O 5 -I/O Mode 0 -I/O 2 -I/O ModeInput Read Register Operation16 Semaphore Operation Example FunctionRange Ambient Temperature Electrical Characteristics for V CC =Maximum Ratings23 Operating RangeStandb y Cur rent One Port Cmos Ind Input Leakage CurrentODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portInput High Voltage 5V any port Input LOW Voltage 5V any port 0V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsInterrupt Timing Busy TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.1 Either Port Address Access36, 37 Switching WaveformsRead Cycle No.2 Either Port CE/OE Access36, 39 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53CER Valid First Busy Timing Diagram No.1 CE Arbitration CEL Valid First54Right Address Valid First Right Side Clears INT R Interrupt Timing Diagrams Left Side Sets INT RRight Side Sets Intl Left Side Clears INT LOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change