Cypress CYDC064B08, CYDC064B16, CYDC256B16, CYDC128B08 Timing Diagram of Read with Busy M/S=HIGH53

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CYDC256B16, CYDC128B16,

CYDC064B16, CYDC128B08,

CYDC064B08

Switching Waveforms (continued)

Timing Diagram of Read with BUSY (M/S=HIGH)[53]

 

tWC

 

ADDRESSR

MATCH

 

R/WR

tPWE

 

 

tSD

tHD

DATA INR

VALID

 

 

tPS

 

ADDRESSL

MATCH

 

 

tBLA

tBHA

BUSYL

 

t

 

 

BDD

 

 

tDDD

DATAOUTL

 

VALID

 

tWDD

 

Write Timing with Busy Input (M/S = LOW)

R/W

BUSY

tWB

tPWE

tWH

Note:

53. CEL = CER = LOW.

Document #: 001-01638 Rev. *E

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Contents Selection Guide for VCC = FeaturesCYDC256B16, CYDC128B16 CYDC064B16, CYDC128B08 CYDC064B08 UnitCYDC256B16, CYDC128B16 Pin Tqfp Top View Pin Configurations 3, 4, 5, 6CYDC064B08 Pin Configurations 7, 8, 9Functional Description Pin DefinitionsBusy InterruptsMaster/Slave Input Read RegisterArchitecture 0 -I/O 5 -I/O Mode 0 -I/O 2 -I/O ModeInput Read Register Operation16 Semaphore Operation Example FunctionRange Ambient Temperature Electrical Characteristics for V CC =Maximum Ratings23 Operating RangeStandb y Cur rent One Port Cmos Ind Input Leakage CurrentODR Output LOW Voltage I OL = 8 mA 5V any port 0V any port Output LOW Voltage I OL = 2 mA 5V any port 0V any portInput High Voltage 5V any port Input LOW Voltage 5V any port 0V any portParameter Description Test Conditions Max Unit CapacitanceWrite Cycle AC7Test Loads and WaveformsBusy Timing Interrupt TimingSemaphore Timing High after Slave Data Hold From Write End Document # 001-01638 Rev. *E SEM Address Access Time Document # 001-01638 Rev. *E Read Cycle No.1 Either Port Address Access36, 37 Switching WaveformsRead Cycle No.2 Either Port CE/OE Access36, 39 Read Cycle No Either Port36, 38, 41Write Cycle No CE Controlled Timing 41, 42, 43 Semaphore Read After Write Timing, Either Side49 Timing Diagram of Semaphore Contention51Write Timing with Busy Input M/S = LOW Timing Diagram of Read with Busy M/S=HIGH53Busy Timing Diagram No.1 CE Arbitration CEL Valid First54 CER Valid FirstRight Address Valid First Right Side Clears INT R Interrupt Timing Diagrams Left Side Sets INT RRight Side Sets Intl Left Side Clears INT LOrdering Information Pin Thin Plastic Quad Flat Pack Tqfp A100 Package DiagramDocument History Issue Date Orig. Description of Change