Cypress CYD18S36V, CYD02S36VA, CYD09S36V, CYD01S36V, CYD04S36V Counter Write, Read Reset Address

Page 20

 

 

 

 

 

 

 

 

 

CYD01S36V

 

 

 

 

 

 

 

CYD02S36V/36VA/CYD04S36V

 

 

 

 

 

 

 

CYD09S36V/CYD18S36V

Switching Waveforms (continued)

Figure 14. Counter Reset [43, 44]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

 

 

 

 

tCH2

tCL2

 

 

 

 

 

 

 

CLK

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

tHA

 

 

ADDRESS

 

 

 

 

 

 

An

 

Am

 

Ap

INTERNAL

A

x

 

 

0

1

A

n

A

m

Ap

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSW

tHW

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

 

 

 

ADS

 

 

 

 

 

 

 

 

 

 

 

CNTEN

 

 

 

 

 

 

 

 

 

 

 

 

tSRST

tHRST

 

 

 

 

 

 

 

 

CNTRST

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSD

tHD

 

 

 

 

 

 

DATAIN

 

 

 

D0

tCD2

tCD2

 

 

 

 

DATAOUT[45]

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Q

 

0

 

Q

Q

 

n

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COUNTER

WRITE

tCKLZ

 

 

 

READ

 

 

 

 

READ

 

READ

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

READ

 

 

 

 

 

 

 

 

 

 

 

 

RESET

ADDRESS 0

ADDRESS 0

 

ADDRESS 1

 

 

 

ADDRESS An

ADDRESS Am

 

 

 

Notes

43.CE0 = BE0 – BE3 = LOW; CE1 = MRST = CNT/MSK = HIGH.

44.No dead cycle exists during counter reset. A Read or Write cycle may be coincidental with the counter reset.

45.Retransmit happens if the counter remains in increment mode after it wraps to initially loaded value

Document Number: 38-06076 Rev. *G

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Contents Seamless Migration to Next-Generation Dual-Port Family FeaturesFunctional Description Logic Block Diagram1 Dual Ported ArrayPin Configurations DQ10R DQ12R DQ14RPin Definitions Address Counter and Mask Register Operations19 Master ResetMailbox Interrupts Counter Reset Operation Counter Load OperationCLK Mrst CNT/MSK Cntrst ADS Cnten Operation DescriptionMask Reset Operation Counter Increment OperationCounter Hold Operation Counter InterruptCounter, Mask, and Mirror Logic Block Diagram1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JTAG23Performing a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit DevicesScan Chain for 18-Mbit Device Scan Register Sizes Register Name Bit SizeInstruction Identification Codes Description ReservedElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceSwitching Characteristics Over the Operating Range Port to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinJtag Switching Waveform Switching WaveformsData OUT CLKAddress Data OUT Read No Operation Write ADDRESSB1Address B2 Datain DataoutRead Write ADSAddress Internal ADS CntenRead Reset Address Counter WriteCLK External Address A0-A16 Internal Address Load Readback Increment External Counter Address InternalCLK L LportLport Data CLK RCounter Interrupt and Retransmit17, 45, 53, 54, 55 CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFFCLK CE0 CE1 ClklLport 7FFFF Address INT ROrdering Information Package Diagrams Ball Fbga 17 x 17 mm BB256Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History REV ECN no
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