Cypress CYD18S36V, CYD02S36VA, CYD09S36V, CYD01S36V Counter, Mask, and Mirror Logic Block Diagram1

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CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Figure 2. Counter, Mask, and Mirror Logic Block Diagram[1]

CNT/MSK

CNTEN

ADS

CNTRST

MRST

Bidirectional

Address

Lines

CLK

Decode

Logic

Mask

Register

Counter/

Address

Register

Address

Decode

RAM Array

	From	17	Load/Increment
	From	17
	Address	Mirror		Counter
	Lines	Mirror	1	Counter	To Readback
	Lines		1		To Readback
			1		and Address
			0		Decode
	From	17	0		Decode
			0

	Mask	Increment
	Register	Logic	Wrap		17

	From	17	17
	From
	Mask	17	Bit 0
	From		Bit 0

		+1		Wrap
	Counter	+1	1	Wrap	Wrap
	Counter		1	Detect	Wrap
		+2	0
		+2	1	17
			1	17	To
					To
			0		Counter
			0

Document Number: 38-06076 Rev. *G

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Contents Seamless Migration to Next-Generation Dual-Port Family FeaturesFunctional Description Logic Block Diagram1 Dual Ported ArrayPin Configurations DQ10R DQ12R DQ14RPin Definitions Address Counter and Mask Register Operations19 Master ResetMailbox Interrupts Counter Reset Operation Counter Load OperationCLK Mrst CNT/MSK Cntrst ADS Cnten Operation DescriptionMask Reset Operation Counter Increment OperationCounter Hold Operation Counter InterruptCounter, Mask, and Mirror Logic Block Diagram1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JTAG23Performing a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit DevicesScan Chain for 18-Mbit Device Scan Register Sizes Register Name Bit SizeInstruction Identification Codes Description ReservedElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceSwitching Characteristics Over the Operating Range Port to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinJtag Switching Waveform Switching WaveformsData OUT CLKAddress Data OUT Read No Operation Write ADDRESSB1Address B2 Datain DataoutRead Write ADSAddress Internal ADS CntenRead Reset Address Counter WriteCLK External Address A0-A16 Internal Address Load Readback Increment External Counter Address InternalCLK L LportLport Data CLK RCounter Interrupt and Retransmit17, 45, 53, 54, 55 CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFFCLK CE0 CE1 ClklLport 7FFFF Address INT ROrdering Information Package Diagrams Ball Fbga 17 x 17 mm BB256Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History REV ECN no