Cypress CYD01S36V, CYD02S36VA, CYD09S36V, CYD18S36V CLK External Address A0-A16 Internal Address

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CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Switching Waveforms (continued)

Figure 15. Readback State of Address Counter or Mask Register[46, 47, 48, 49]

CLK

EXTERNAL

ADDRESS A0–A16

INTERNAL ADDRESS

	tCYC2
	tCH2	tCL2
tSA	tHA	tCA2 or tCM2
An		An*

An+1

An+2

An+3

An+4

tSAD

HAD

tSCN

tHCN

CNTEN

tCD2

tCKHZ

DATAOUT

Qx-2

Qx-1

LOAD READBACK INCREMENT

EXTERNAL COUNTER

ADDRESS INTERNAL

ADDRESS

tCKLZ

Qn+1 Qn+2 Qn+3

Notes

46.CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

47.Address in output mode. Host must not be driving address bus after tCKLZ in next clock cycle.

48.Address in input mode. Host can drive address bus after tCKHZ.

49.An * is the internal value of the address counter (or the mask register depending on the CNT/MSK level) being Read out on the address lines.

Document Number: 38-06076 Rev. *G

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Contents Features Functional DescriptionSeamless Migration to Next-Generation Dual-Port Family Dual Ported Array Logic Block Diagram1DQ10R DQ12R DQ14R Pin ConfigurationsPin Definitions Master Reset Mailbox InterruptsAddress Counter and Mask Register Operations19 Counter Load Operation Counter Reset OperationCLK Mrst CNT/MSK Cntrst ADS Cnten Operation DescriptionCounter Increment Operation Mask Reset OperationCounter Hold Operation Counter InterruptCounter, Mask, and Mirror Logic Block Diagram1 Ieee 1149.1 Serial Boundary Scan JTAG23 Performing a TAP ResetPerforming a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit DevicesScan Register Sizes Register Name Bit Size Scan Chain for 18-Mbit DeviceReserved Instruction Identification Codes DescriptionMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range CapacitanceSwitching Characteristics Over the Operating Range Master Reset Timing Port to Port DelaysJtag Timing Parameter Description 167/133/100 Unit MinSwitching Waveforms Jtag Switching WaveformCLK AddressData OUT ADDRESSB1 Address B2Data OUT Read No Operation Write Dataout DatainRead Write ADSADS Cnten Address InternalCounter Write Read Reset AddressLoad Readback Increment External Counter Address Internal CLK External Address A0-A16 Internal AddressLport CLK LLport Data CLK RCNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFF Counter Interrupt and Retransmit17, 45, 53, 54, 55Clkl CLK CE0 CE1Lport 7FFFF Address INT ROrdering Information Ball Fbga 17 x 17 mm BB256 Package DiagramsBall Fbga 23 mm x 23 mm x 1.7 mm BB256B Worldwide Sales and Design Support Products PSoC Solutions Sales, Solutions and Legal InformationDocument History REV ECN no