Cypress CYD01S36V, CYD02S36VA, CYD09S36V, CYD18S36V manual Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B

Page 27

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Package Diagrams (continued)

Figure 20. 256-ball FBGA (23 mm x 23 mm x 1.7 mm) BB256B

TOP VIEW

PIN 1 CORNER

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

 

0.70±0.05

0.25 C

 

 

 

 

 

 

 

 

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.70 MAX.

 

0.15 C

 

 

 

 

 

 

 

 

 

 

23.00±0.10

B

 

 

 

 

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.25 M C A

B

 

 

 

 

 

 

 

PIN 1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.50

+0.10

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(256X)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

-0.05

 

 

 

 

 

 

 

 

 

 

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

 

A

 

B

 

C

1.00

D

E

 

 

F

 

G

15.00

H

J

 

K

 

L

7.50

M

N

 

 

P

 

R

 

T

 

1.00

 

7.50

 

15.00

A

23.00±0.10

0.20(4X)

 

0.56

SEATING PLANE

C

JEDEC MO-192

+0.10 0.35 -0.05

51-85201-*A

Document Number: 38-06076 Rev. *G

Page 27 of 28

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Contents Features Functional DescriptionSeamless Migration to Next-Generation Dual-Port Family Dual Ported Array Logic Block Diagram1DQ10R DQ12R DQ14R Pin ConfigurationsPin Definitions Master Reset Mailbox InterruptsAddress Counter and Mask Register Operations19 Operation Description Counter Reset OperationCounter Load Operation CLK Mrst CNT/MSK Cntrst ADS CntenCounter Interrupt Mask Reset OperationCounter Increment Operation Counter Hold OperationCounter, Mask, and Mirror Logic Block Diagram1 Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Performing a TAP ResetIeee 1149.1 Serial Boundary Scan JTAG23 Performing a Pause/RestartScan Register Sizes Register Name Bit Size Scan Chain for 18-Mbit DeviceReserved Instruction Identification Codes DescriptionCapacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeSwitching Characteristics Over the Operating Range Parameter Description 167/133/100 Unit Min Port to Port DelaysMaster Reset Timing Jtag TimingSwitching Waveforms Jtag Switching WaveformCLK AddressData OUT ADDRESSB1 Address B2Data OUT Read No Operation Write ADS DatainDataout Read WriteADS Cnten Address InternalCounter Write Read Reset AddressLoad Readback Increment External Counter Address Internal CLK External Address A0-A16 Internal AddressCLK R CLK LLport Lport DataCNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFF Counter Interrupt and Retransmit17, 45, 53, 54, 55INT R CLK CE0 CE1Clkl Lport 7FFFF AddressOrdering Information Ball Fbga 17 x 17 mm BB256 Package DiagramsBall Fbga 23 mm x 23 mm x 1.7 mm BB256B REV ECN no Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History