Cypress CYD02S36VA, CYD09S36V, CYD18S36V manual CLK CE0 CE1, Clkl, Lport 7FFFF Address, Int R, Clkr

CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Switching Waveforms (continued)

Figure 18. MailBox Interrupt Timing[57, 58, 59, 60, 61]

	tCYC2
tCH2	tCL2
CLKL
	tSA	tHA
L_PORT	7FFFF		An
ADDRESS
			tSINT

An+1

An+2 An+3

INTR

tCYC2

tCH2 tCL2

CLKR

tSA tHA

tRINT

R_PORT	Am	Am+1	7FFFF	Am+3	Am+4
ADDRESS

Table 7. Read/Write and Enable Operation (Any Port)[1, 18, 62, 63, 64]

			Inputs				Outputs	Operation
OE	CLK			CE0	CE1	R/W	DQ0 – DQ35
X				H	X	X	High-Z	Deselected
X				X	L	X	High-Z	Deselected
X				L	H	L	DIN	Write
L				L	H	H	DOUT	Read
H		X		L	H	X	High-Z	Outputs Disabled

Notes

57.CE0 = OE = ADS = CNTEN = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.

58.Address “7FFFF” is the mailbox location for R_Port of the 9-Mbit device.

59.L_Port is configured for Write operation, and R_Port is configured for Read operation.

60.At least one byte enable (BE0 – BE3) is required to be active during interrupt operations.

61.Interrupt flag is set with respect to the rising edge of the Write clock, and is reset with respect to the rising edge of the Read clock.

62.OE is an asynchronous input signal.

63.When CE changes state, deselection and Read happen after one cycle of latency.

64.CE0 = OE = LOW; CE1 = R/W = HIGH.

Document Number: 38-06076 Rev. *G Page 24 of 28

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