Cypress CYD02S36VA, CYD09S36V, CYD18S36V manual Clk L, Lport Data, Clk R, Rport Data OUT

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CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Switching Waveforms (continued)

Figure 16. Left_Port (L_Port) Write to Right_Port (R_Port) Read[50, 51, 52]

 

 

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKL

 

 

tCH2

 

 

 

 

 

 

 

tCL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

L_PORT

 

 

 

 

 

 

 

 

 

 

 

 

tSA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

An

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/WL

tSW

tHW

 

 

 

 

tCKHZ

tSD

tHD

tCKLZ

L_PORT

 

 

Dn

 

DATAIN

 

 

 

 

 

 

 

 

 

 

 

 

tCYC2

 

 

 

 

 

 

 

 

 

 

tCCS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLKR

 

 

 

 

 

 

 

 

 

 

 

 

tCL2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tCH2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R_PORT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tSA

 

 

 

 

 

 

 

 

 

 

 

 

 

tHA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

An

 

 

 

ADDRESS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R/WR

 

 

tCD2

R_PORT

Qn

DATAOUT

 

tDC

Notes

50.CE0 = OE = ADS = CNTEN = BE0 – BE3 = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH.

51.This timing is valid when one port is writing, and other port is reading the same location at the same time. If tCCS is violated, indeterminate data is Read out.

52.If tCCS < minimum specified value, then R_Port Reads the most recent data (written by L_Port) only (2 * tCYC2 + tCD2) after the rising edge of R_Port's clock. If tCCS > minimum specified value, then R_Port Reads the most recent data (written by L_Port) (tCYC2 + tCD2) after the rising edge of R_Port's clock.

Document Number: 38-06076 Rev. *G

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Contents Functional Description FeaturesSeamless Migration to Next-Generation Dual-Port Family Logic Block Diagram1 Dual Ported ArrayPin Configurations DQ10R DQ12R DQ14RPin Definitions Mailbox Interrupts Master ResetAddress Counter and Mask Register Operations19 CLK Mrst CNT/MSK Cntrst ADS Cnten Counter Reset OperationCounter Load Operation Operation DescriptionCounter Hold Operation Mask Reset OperationCounter Increment Operation Counter InterruptCounter, Mask, and Mirror Logic Block Diagram1 Performing a Pause/Restart Performing a TAP ResetIeee 1149.1 Serial Boundary Scan JTAG23 Boundary Scan Hierarchy for 9-Mbit and 18-Mbit DevicesScan Chain for 18-Mbit Device Scan Register Sizes Register Name Bit SizeInstruction Identification Codes Description ReservedOperating Range Electrical Characteristics Over the Operating RangeMaximum Ratings CapacitanceSwitching Characteristics Over the Operating Range Jtag Timing Port to Port DelaysMaster Reset Timing Parameter Description 167/133/100 Unit MinJtag Switching Waveform Switching WaveformsAddress CLKData OUT Address B2 ADDRESSB1Data OUT Read No Operation Write Read Write DatainDataout ADSAddress Internal ADS CntenRead Reset Address Counter WriteCLK External Address A0-A16 Internal Address Load Readback Increment External Counter Address InternalLport Data CLK LLport CLK RCounter Interrupt and Retransmit17, 45, 53, 54, 55 CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFFLport 7FFFF Address CLK CE0 CE1Clkl INT ROrdering Information Package Diagrams Ball Fbga 17 x 17 mm BB256Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B Document History Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions REV ECN no
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