Cypress CYD02S36VA manual Maximum Ratings, Electrical Characteristics Over the Operating Range

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CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Maximum Ratings

Exceeding maximum ratings[25] may shorten the useful life of the device. User guidelines are not tested.

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

Power Applied

–55°C to +125°C

Supply Voltage to Ground Potential

–0.5V to +4.6V

DC Voltage Applied to

 

Outputs in High-Z State

–0.5V to VDD +0.5V

DC Input Voltage

–0.5V to VDD + 0.5V[26]

Electrical Characteristics Over the Operating Range

Output Current into Outputs (LOW)

20 mA

Static Discharge Voltage

 

> 2000V

(JEDEC JESD22-A114-2000B)

 

 

Latch-up Current

 

> 200 mA

Operating Range

 

 

 

 

 

 

Range

Ambient

VDDIO/VTTL

[13]

Temperature

VCORE

Commercial

0°C to +70°C

3.3V±165 mV

1.8V±100 mV

 

 

 

 

Industrial

–40°C to +85°C

3.3V±165 mV

1.8V±100 mV

 

 

 

 

Parameter

 

Description

 

 

-167

 

-133

 

 

-100

 

Unit

 

 

 

 

Min

Typ.

Max

Min

Typ.

Max

Min

Typ.

Max

 

VOH

Output HIGH Voltage (VDD = Min, IOH= –4.0 mA)

2.4

 

 

2.4

 

 

 

2.4

 

 

V

 

VOL

Output LOW Voltage (VDD = Min, IOL= +4.0 mA)

 

 

 

0.4

 

 

0.4

 

 

 

0.4

V

 

VIH

Input HIGH Voltage

 

 

 

2.0

 

 

2.0

 

 

 

2.0

 

 

V

 

VIL

Input LOW Voltage

 

 

 

 

 

 

0.8

 

 

0.8

 

 

 

0.8

V

 

IOZ

Output Leakage Current

 

 

 

–10

 

10

–10

 

10

 

–10

 

10

μA

 

IIX1

Input Leakage Current Except TDI, TMS,

MRST

–10

 

10

–10

 

10

 

–10

 

10

μA

 

IIX2

Input Leakage Current TDI, TMS, MRST

–1.0

 

0.1

–1.0

 

0.1

 

–1.0

 

0.1

mA

 

ICC

Operating Current for

 

CYD01S36V

 

 

225

300

 

225

300

 

 

 

 

mA

 

 

(VDD = Max.,IOUT = 0 mA), Outputs

CYD02S36V/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Disabled

 

 

CYD02S36VA/

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYD04S36V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CYD09S36V

 

 

450

600

 

370

540

 

 

 

 

mA

 

ISB1[27]

 

 

 

CYD18S36V

 

 

 

 

 

410

580

 

 

315

450

mA

 

Standby Current (Both Ports TTL Level)

 

 

90

115

 

90

115

 

 

 

 

mA

 

ISB2[27]

CEL and CER VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Standby Current (One Port TTL Level)

 

 

160

210

 

160

210

 

 

 

 

mA

 

ISB3[27]

CEL CER VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Standby Current (Both Ports CMOS Level)

 

 

55

75

 

55

75

 

 

 

 

mA

 

ISB4[27]

CEL and CER VDD – 0.2V, f = 0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Standby Current (One Port CMOS Level)

 

 

160

210

 

160

210

 

 

 

 

mA

 

 

CEL CER VIH, f = fMAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ISB5

Operating Current (VDDIO = Max,

CYD18S36V

 

 

 

 

 

 

75

 

 

 

75

mA

 

ICORE[13]

Iout = 0 mA, f = 0) Outputs Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Core Operating Current for (VDD = Max, IOUT = 0 mA),

 

 

0

0

 

0

0

 

 

0

0

mA

 

 

Outputs Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Capacitance

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Part Number

Parameter[28]

 

Description

 

 

 

Test Conditions

 

 

Max

Unit

 

CYD01S36/

 

CIN

Input Capacitance

 

TA = 25°C, f = 1 MHz,

 

 

13

pF

 

CYD02S36V/36VA/

 

 

 

 

 

VDD = 3.3V

 

 

 

 

 

 

 

 

 

CYD04S36V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

COUT

Output Capacitance

 

 

 

 

 

 

 

 

10

pF

 

CYD09S36V

CIN

Input Capacitance

 

 

 

 

 

 

 

 

22

pF

 

 

 

COUT

Output Capacitance

 

 

 

 

 

 

 

 

10[29]

pF

 

CYD18S36V

CIN

Input Capacitance

 

 

 

 

 

 

 

 

40

pF

 

 

 

COUT

Output Capacitance

 

 

 

 

 

 

 

 

20

pF

 

Notes

25.The voltage on any input or IO pin cannot exceed the power pin during power up.

26.Pulse width < 20 ns.

27.ISB1, ISB2, ISB3 and ISB4 are not applicable for CYD18S36V because it cannot be powered down by using chip enable pins.

28.COUT also references CIO.

29.Except INT and CNTINT which are 20 pF.

Document Number: 38-06076 Rev. *G

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Contents Features Functional DescriptionSeamless Migration to Next-Generation Dual-Port Family Logic Block Diagram1 Dual Ported ArrayPin Configurations DQ10R DQ12R DQ14RPin Definitions Master Reset Mailbox InterruptsAddress Counter and Mask Register Operations19 Counter Reset Operation Counter Load OperationCLK Mrst CNT/MSK Cntrst ADS Cnten Operation DescriptionMask Reset Operation Counter Increment OperationCounter Hold Operation Counter InterruptCounter, Mask, and Mirror Logic Block Diagram1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JTAG23Performing a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit DevicesScan Chain for 18-Mbit Device Scan Register Sizes Register Name Bit SizeInstruction Identification Codes Description ReservedElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceSwitching Characteristics Over the Operating Range Port to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinJtag Switching Waveform Switching WaveformsCLK AddressData OUT ADDRESSB1 Address B2Data OUT Read No Operation Write Datain DataoutRead Write ADSAddress Internal ADS CntenRead Reset Address Counter WriteCLK External Address A0-A16 Internal Address Load Readback Increment External Counter Address InternalCLK L LportLport Data CLK RCounter Interrupt and Retransmit17, 45, 53, 54, 55 CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFFCLK CE0 CE1 ClklLport 7FFFF Address INT ROrdering Information Package Diagrams Ball Fbga 17 x 17 mm BB256Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History REV ECN no