Cypress CYD09S36V manual Counter Increment Operation, Counter Hold Operation, Counter Interrupt

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CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Counter Increment Operation

Once the address counter register is initially loaded with an external address, the counter can internally increment the address value, potentially addressing the entire memory array. Only the unmasked bits of the counter register are incremented. The corresponding bit in the mask register must be a “1” for a counter bit to change. The counter register is incremented by 1 if the least significant bit is unmasked, and by 2 if it is masked. If all unmasked bits are “1,” the next increment wraps the counter back to the initially loaded value. If an Increment results in all the unmasked bits of the counter being “1s,” a counter interrupt flag (CNTINT) is asserted. The next Increment returns the counter register to its initial value, which was stored in the mirror register. The counter address can instead be forced to loop to 00000 by externally connecting CNTINT to CNTRST.[21] An increment that results in one or more of the unmasked bits of the counter being “0” de-asserts the counter interrupt flag. The example in Figure 3 on page 9 shows the counter mask register loaded with a mask value of 0003Fh unmasking the first 6 bits with bit “0” as the LSB and bit “16” as the MSB. The maximum value the mask register can be loaded with is 3FFFFh. Setting the mask register to this value allows the counter to access the entire memory space. The address counter is then loaded with an initial value of 8h. The base address bits (in this case, the 6th address through the 16th address) are loaded with an address value but do not increment once the counter is configured for increment operation. The counter address starts at address 8h. The counter increments its internal address value till it reaches the mask register value of 3Fh. The counter wraps around the memory block to location 8h at the next count. CNTINT is issued when the counter reaches its maximum value.

Counter Hold Operation

The value of all three registers can be constantly maintained unchanged for an unlimited number of clock cycles. Such operation is useful in applications where wait states are needed, or when address is available a few cycles ahead of data in a shared bus interface.

Counter Interrupt

The counter interrupt (CNTINT) is asserted LOW when an increment operation results in the unmasked portion of the counter register being all “1s.” It is deasserted HIGH when an Increment operation results in any other value. It is also de-asserted by Counter Reset, Counter Load, Mask Reset and Mask Load operations, and by MRST.

Counter Readback Operation

The internal value of the counter register can be read out on the address lines. Readback is pipelined; the address is valid tCA2

after the next rising edge of the port’s clock. If address readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) are three-stated. Figure 2 on page 8 shows a block diagram of the operation.

Retransmit

Retransmit is a feature that allows the Read of a block of memory more than once without the need to reload the initial address. This eliminates the need for external logic to store and route data. It also reduces the complexity of the system design and saves board space. An internal “mirror register” is used to store the initially loaded address counter value. When the counter unmasked portion reaches its maximum value set by the mask register, it wraps back to the initial value stored in this “mirror register.” If the counter is continuously configured in increment mode, it increments again to its maximum value and wraps back to the value initially stored into the “mirror register.” Thus, the repeated access of the same data is allowed without the need for any external logic.

Mask Reset Operation

The mask register is reset to all “1s,” which unmasks every bit of the counter. Master reset (MRST) also resets the mask register to all “1s.”

Mask Load Operation

The mask register is loaded with the address value presented at the address lines. Not all values permit correct increment opera- tions. Permitted values are of the form 2n – 1 or 2n – 2. From the most significant bit to the least significant bit, permitted values have zero or more “0s,” one or more “1s,” or one “0.” Thus 7FFFF, 003FE, and 00001 are permitted values, but 7F0FF, 003FC, and 00000 are not.

Mask Readback Operation

The internal value of the mask register can be read out on the address lines. Readback is pipelined; the address is valid tCM2 after the next rising edge of the port’s clock. If mask readback occurs while the port is enabled (CE0 LOW and CE1 HIGH), the data lines (DQs) are three-stated. Figure 2 on page 8 shows a block diagram of the operation.

Counting by Two

When the least significant bit of the mask register is “0,” the counter increments by two. This may be used to connect the x36 devices as a 72-bit single port SRAM in which the counter of one port counts even addresses and the counter of the other port counts odd addresses. This even-odd address scheme stores one half of the 72-bit data in even memory locations, and the other half in odd memory locations.

Note

21. CNTINT and CNTRST specs are guaranteed by design to operate properly at speed grade operating frequency when tied together.

Document Number: 38-06076 Rev. *G

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Contents Functional Description FeaturesSeamless Migration to Next-Generation Dual-Port Family Dual Ported Array Logic Block Diagram1DQ10R DQ12R DQ14R Pin ConfigurationsPin Definitions Mailbox Interrupts Master ResetAddress Counter and Mask Register Operations19 Operation Description Counter Reset OperationCounter Load Operation CLK Mrst CNT/MSK Cntrst ADS CntenCounter Interrupt Mask Reset OperationCounter Increment Operation Counter Hold OperationCounter, Mask, and Mirror Logic Block Diagram1 Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Performing a TAP ResetIeee 1149.1 Serial Boundary Scan JTAG23 Performing a Pause/RestartScan Register Sizes Register Name Bit Size Scan Chain for 18-Mbit DeviceReserved Instruction Identification Codes DescriptionCapacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeSwitching Characteristics Over the Operating Range Parameter Description 167/133/100 Unit Min Port to Port DelaysMaster Reset Timing Jtag TimingSwitching Waveforms Jtag Switching WaveformAddress CLKData OUT Address B2 ADDRESSB1Data OUT Read No Operation Write ADS DatainDataout Read WriteADS Cnten Address InternalCounter Write Read Reset AddressLoad Readback Increment External Counter Address Internal CLK External Address A0-A16 Internal AddressCLK R CLK LLport Lport DataCNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFF Counter Interrupt and Retransmit17, 45, 53, 54, 55INT R CLK CE0 CE1Clkl Lport 7FFFF AddressOrdering Information Ball Fbga 17 x 17 mm BB256 Package DiagramsBall Fbga 23 mm x 23 mm x 1.7 mm BB256B REV ECN no Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History
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