Cypress CYD04S36V, CYD02S36VA, CYD09S36V ADDRESSB1, Address B2, Data OUT Read No Operation Write

						CYD01S36V
				CYD02S36V/36VA/CYD04S36V
					CYD09S36V/CYD18S36V
Switching Waveforms (continued)			Figure 9. Bank Select Read[37, 38]
	tCH2	tCYC2
		tCL2
CLK
	tSA	tHA
ADDRESS(B1)	A0	A1	A2	A3	A4	A5

	tSC	tHC
CE(B1)
			tCD2	tSC		tHC	tCD2	tCKHZ	tCD2	tCKHZ
DATAOUT(B1)				Q	0		Q			Q3
	tSA	tHA					1
						tDC	tDC		tCKLZ
ADDRESS(B2)	A0		A1		A2		A3	A4		A5
				tSC			tHC
CE(B2)
DATAOUT(B2)	tSC	tHC						tCD2	tCKHZ	tCD2
								Q2		Q4
							tCKLZ			tCKLZ
		Figure 10. Read-to-Write-to-Read (OE = LOW)[36, 39, 40, 41, 42]
	tCH2	tCYC2	tCL2
CLK
CE
tSC		tHC

	tSW		tHW
R/W
tSW	tHW
An	An+1	An+2	An+2	An+2	An+3
ADDRESS				tSD tHD
tSA	tHA
DATA	tCD2			Dn+2
IN		tDC	tCKHZ
DATAOUT	Qn
	READ		NO OPERATION		WRITE

Notes

37.In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress FLEx36 device from this data sheet. ADDRESS(B1) = ADDRESS(B2).

38.ADS = CNTEN= BE0 – BE3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.

39.Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.

40.During “No Operation,” data in memory at the selected address may be corrupted and must be rewritten to ensure data integrity.

41.CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

42.CE0 = BE0 – BE3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be completed (labelled as no operation). One clock cycle is required to three-state the IO for the Write operation on the next rising edge of CLK.

Document Number: 38-06076 Rev. *G Page 17 of 28

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