Cypress CYD02S36VA, CYD09S36V, CYD18S36V, CYD01S36V, CYD04S36V manual Clk, Address, Data OUT

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CYD01S36V

CYD02S36V/36VA/CYD04S36V

CYD09S36V/CYD18S36V

Switching Waveforms (continued)

Figure 8. Read Cycle[14, 33, 34, 35, 36]

tCYC2

CLK

tCH2

tCL2

CE

tSC

tHC

tSC

tHC

tSB

tHB

BE0–BE3

R/W
	tSW	tHW
ADDRESS	tSA	tHA
ADDRESS	An	An+1	An+2		An+3
	An	An+1	An+2		An+3
DATAOUT		1 Latency	tCD2	tDC
DATAOUT			Qn	Qn+1	Qn+2
			Qn	Qn+1	Qn+2
		tCKLZ		tOHZ	tOLZ
		tCKLZ			tOLZ
OE					tOE
					tOE

Notes

33.OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.

34.ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.

35.The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.

36.Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK. Numbers are for reference only.

Document Number: 38-06076 Rev. *G

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Contents Functional Description FeaturesSeamless Migration to Next-Generation Dual-Port Family Logic Block Diagram1 Dual Ported ArrayPin Configurations DQ10R DQ12R DQ14RPin Definitions Mailbox Interrupts Master ResetAddress Counter and Mask Register Operations19 Counter Reset Operation Counter Load OperationCLK Mrst CNT/MSK Cntrst ADS Cnten Operation DescriptionMask Reset Operation Counter Increment OperationCounter Hold Operation Counter InterruptCounter, Mask, and Mirror Logic Block Diagram1 Performing a TAP Reset Ieee 1149.1 Serial Boundary Scan JTAG23Performing a Pause/Restart Boundary Scan Hierarchy for 9-Mbit and 18-Mbit DevicesScan Chain for 18-Mbit Device Scan Register Sizes Register Name Bit SizeInstruction Identification Codes Description ReservedElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range CapacitanceSwitching Characteristics Over the Operating Range Port to Port Delays Master Reset TimingJtag Timing Parameter Description 167/133/100 Unit MinJtag Switching Waveform Switching WaveformsAddress CLKData OUT Address B2 ADDRESSB1Data OUT Read No Operation Write Datain DataoutRead Write ADSAddress Internal ADS CntenRead Reset Address Counter WriteCLK External Address A0-A16 Internal Address Load Readback Increment External Counter Address InternalCLK L LportLport Data CLK RCounter Interrupt and Retransmit17, 45, 53, 54, 55 CNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFFCLK CE0 CE1 ClklLport 7FFFF Address INT ROrdering Information Package Diagrams Ball Fbga 17 x 17 mm BB256Ball Fbga 23 mm x 23 mm x 1.7 mm BB256B Sales, Solutions and Legal Information Worldwide Sales and Design Support Products PSoC SolutionsDocument History REV ECN no