Cypress CYD04S36V, CYD02S36VA, CYD09S36V manual Counter Interrupt and Retransmit17, 45, 53, 54, 55

Page 23

 

 

 

 

 

 

 

CYD01S36V

 

 

 

 

 

 

CYD02S36V/36VA/CYD04S36V

 

 

 

 

 

 

CYD09S36V/CYD18S36V

Switching Waveforms (continued)

 

 

 

 

 

 

 

Figure 17. Counter Interrupt and Retransmit[17, 45, 53, 54, 55, 56]

 

 

 

 

tCYC2

 

 

 

 

 

 

tCH2

tCL2

 

 

 

 

CLK

 

 

 

 

 

 

 

 

tSCM

tHCM

 

 

 

 

CNT/MSK

 

 

 

 

 

 

 

ADS

 

 

 

 

 

 

 

CNTEN

 

 

 

 

 

 

 

COUNTER

 

 

 

 

 

 

 

INTERNAL

3FFFC

3FFFD

3FFFE

3FFFF

Last_Loaded

Last_Loaded +1

ADDRESS

 

 

 

 

tRCINT

 

 

 

 

 

tSCINT

 

CNTINT

 

 

 

 

 

 

 

Notes

53.CE0 = OE = BE0 – BE3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.

54.CNTINT is always driven.

55.CNTINT goes LOW when the unmasked portion of the address counter is incremented to the maximum value.

56.The mask register assumed to have the value of 3FFFFh.

Document Number: 38-06076 Rev. *G

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Contents Seamless Migration to Next-Generation Dual-Port Family FeaturesFunctional Description Dual Ported Array Logic Block Diagram1DQ10R DQ12R DQ14R Pin ConfigurationsPin Definitions Address Counter and Mask Register Operations19 Master ResetMailbox Interrupts Operation Description Counter Reset OperationCounter Load Operation CLK Mrst CNT/MSK Cntrst ADS CntenCounter Interrupt Mask Reset OperationCounter Increment Operation Counter Hold OperationCounter, Mask, and Mirror Logic Block Diagram1 Boundary Scan Hierarchy for 9-Mbit and 18-Mbit Devices Performing a TAP ResetIeee 1149.1 Serial Boundary Scan JTAG23 Performing a Pause/RestartScan Register Sizes Register Name Bit Size Scan Chain for 18-Mbit DeviceReserved Instruction Identification Codes DescriptionCapacitance Electrical Characteristics Over the Operating RangeMaximum Ratings Operating RangeSwitching Characteristics Over the Operating Range Parameter Description 167/133/100 Unit Min Port to Port DelaysMaster Reset Timing Jtag TimingSwitching Waveforms Jtag Switching WaveformData OUT CLKAddress Data OUT Read No Operation Write ADDRESSB1Address B2 ADS DatainDataout Read WriteADS Cnten Address InternalCounter Write Read Reset AddressLoad Readback Increment External Counter Address Internal CLK External Address A0-A16 Internal AddressCLK R CLK LLport Lport DataCNT/MSK ADS Cnten Counter Internal 3FFFC 3FFFD 3FFFE 3FFFF Counter Interrupt and Retransmit17, 45, 53, 54, 55INT R CLK CE0 CE1Clkl Lport 7FFFF AddressOrdering Information Ball Fbga 17 x 17 mm BB256 Package DiagramsBall Fbga 23 mm x 23 mm x 1.7 mm BB256B REV ECN no Sales, Solutions and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History