Cypress CY7C65113C manual bit Data Stack Pointer DSP, Address Modes, MOV A, Dspinit

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CY7C65113C

5.58-bit Data Stack Pointer (DSP)

The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP.

During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address 0xFF). This writes data to the memory area reserved for USB endpoint FIFOs. Therefore, the DSP should be indexed at an appropriate memory location that does not compromise the Program Stack, user-defined memory (variables), or the USB endpoint FIFOs.

For USB applications, the firmware should set the DSP to an appropriate location to avoid a memory conflict with RAM dedicated to USB FIFOs. The memory requirements for the USB endpoints are described in Section 17.2. Example assembly instructions to do this with two device addresses (FIFOs begin at 0xD8) are shown below:

MOV A,20h ; Move 20 hex into Accumulator (must be D8h or less) SWAP A,DSP ; swap accumulator value into DSP register.

5.6Address Modes

The CY7C65113 microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed.

5.6.1Data (Immediate)

“Data” address mode refers to a data operand that is actually a constant encoded in the instruction. As an example, consider the instruction that loads A with the constant 0xD8:

• MOV A, 0D8h.

This instruction requires two bytes of code where the first byte identifies the “MOV A” instruction with a data operand as the second byte. The second byte of the instruction is the constant “0xD8.” A constant may be referred to by name if a prior “EQU” statement assigns the constant value to the name. For example, the following code is equivalent to the example shown above:

DSPINIT: EQU 0D8h

MOV A, DSPINIT.

5.6.2Direct

“Direct” address mode is used when the data operand is a variable stored in SRAM. In that case, the one byte address of the variable is encoded in the instruction. As an example, consider an instruction that loads A with the contents of memory address location 0x10:

• MOV A, [10h].

Normally, variable names are assigned to variable addresses using “EQU” statements to improve the readability of the assembler source code. As an example, the following code is equivalent to the example shown above:

buttons: EQU 10h

MOV A, [buttons].

5.6.3Indexed

“Indexed” address mode allows the firmware to manipulate arrays of data stored in SRAM. The address of the data operand is the sum of a constant encoded in the instruction and the contents of the “X” register. Normally, the constant is the “base” address of an array of data and the X register contains an index that indicates which element of the array is actually addressed:

array: EQU 10h

MOV X, 3

MOV A, [X+array].

This would have the effect of loading A with the fourth element of the SRAM “array” that begins at address 0x10. The fourth element would be at address 0x13.

Document #: 38-08002 Rev. *D

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Contents USB Hub with Microcontroller Cypress Semiconductor CorporationCY7C65113C 18.0 16.017.0 19.0List of Tables Features I2C Functional OverviewGpio USBLogic Block Diagram Pin Assignments Pin ConfigurationsProduct Summary Tables Top View CY7C65113C 28-pin SoicI/O Register Summary Mnemonic Instruction Set SummaryInstruction Set Summary Operand Opcode CyclesProgramming Model 14-bit Program CounterProgram Memory begins here KB -32 Prom ends here CY7C65113C8-bit Program Stack Pointer PSP 8-bit Accumulator a8-bit Temporary Register MOV A, Dspinit 8-bit Data Stack Pointer DSPAddress Modes Xtalout Power-on ResetClocking XtalinSuspend Mode Watchdog ResetPort 0 Data Address General-purpose I/O PortsPort 0,1 Low Isink Gpio Configuration Port Gpio Configuration AddressPort 0 Interrupt Enable 10.0 12-bit Free-Running TimerGpio Interrupt Enable Ports Timer MSB Address 11.0 I2C Configuration RegisterTimer LSB Address 2C Configuration Address2C Status and Control Address 12.0 I2C-compatible ControllerI2C Data Address ACKContinue/Busy Write 1 to indicate ready for next transaction IRQ Processor Status and Control RegisterProcessor Status and Control Address 0xFF Interrupts Global Interrupt Enable Register AddressUSB Endpoint Interrupt Enable Address Interrupt Controller Function Diagram Interrupt VectorsInterrupt Latency USB Bus Reset InterruptTimer Interrupt Gpio Interrupt USB Endpoint InterruptsUSB Hub Interrupt 14.8 I2C InterruptUSB Enumeration USB OverviewUSB Serial Interface Engine SIE ACK/NAK/STALLHub Ports Connect Status Connecting/Disconnecting a USB DeviceUSB Hub Enabling/Disabling a USB Device Hub Ports Enable Register AddressHub Ports Enable Register Hub Downstream Ports Status and ControlHub Ports SE0 Status Address 0x4F Hub Downstream Ports Control Register Address 0x4BHub Ports Force Low Hub Ports Data Register Downstream Port Suspend and ResumeHub Ports Data Hub Ports Suspend Address 0x4DUSB Status and Control Address 0x1F USB Upstream Port Status and ControlHub Ports Resume Address 0x4E USB Device Endpoints USB Serial Interface Engine OperationUSB Device Addresses USB Device Address Device A, B Addresses 0x10A and 0x40BSize Label Start Address USB Control Endpoint Mode RegistersUSB Device Endpoint Zero Mode A0, B0 USB Endpoint Counter Registers USB Non-control Endpoint Mode RegistersUSB Non-control Device Endpoint Mode StallUpdate Endpoint Mode/Count Registers Update and Locking MechanismSetup Set Update only if Fifo is WrittenData Data SetUSB Mode Tables Setup OUTDtog Dval Count Dtog Dval Count Endpoint Register Summary PortsLOW Sample Schematic Absolute Maximum RatingsUSB Interface Electrical CharacteristicsParameter Description Conditions Min Max Unit General Upstream/Downstream PortTimer Signals Switching Characteristics fOSC = 6.0 MHzUSB Full-speed Signaling10 Parameter Description Min Max Unit Clock SourceOrdering Code Prom Size Package Type Operating Range Package DiagramOrdering Information CY7C65113C-SXCTREV ECN no Issue Date Orig. Description of ChangeDocument History