Cypress CY7C65113C manual USB Control Endpoint Mode Registers, Size Label Start Address

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CY7C65113C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table 17-1. Memory Allocation for Endpoints

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USB Status And Control Register (0x1F) Bits [7, 6]

 

 

 

 

 

 

 

 

[0,0]

 

 

 

 

[1,0]

 

 

[0,1]

 

 

 

[1,1]

 

 

 

Two USB Addresses:

Two USB Addresses:

One USB Address:

 

One USB Address:

 

 

A (3 Endpoints) and

A (3 Endpoints) and

 

 

 

 

B (2 Endpoints)

 

 

 

B (2 Endpoints)

 

A (5 Endpoints)

 

A (5 Endpoints)

 

 

Label

 

Start Address

Size

Label

Start Address

Size

Label

Start Address

 

Size

Label

 

Start Address

Size

EPB1

 

 

0xD8

8

 

EPB0

0xA8

8

EPA4

0xD8

 

8

EPA3

 

0xA8

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EPB0

 

 

0xE0

8

 

EPB1

0xB0

8

EPA3

0xE0

 

8

EPA4

 

0xB0

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EPA2

 

 

0xE8

8

 

EPA0

0xB8

8

EPA2

0xE8

 

8

EPA0

 

0xB8

 

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EPA1

 

 

0xF0

8

 

EPA1

0xC0

32

EPA1

0xF0

 

8

EPA1

 

0xC0

 

32

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

EPA0

 

 

0xF8

8

 

EPA2

0xE0

32

EPA0

0xF8

 

8

EPA2

 

0xE0

 

32

 

When the SIE writes data to a FIFO, the internal data bus is driven by the SIE; not the CPU. This causes a short delay in the CPU operation. The delay is three clock cycles per byte. For example, an 8-byte data write by the SIE to the FIFO generates a delay of 2 s (3 cycles/byte * 83.33 ns/cycle * 8 bytes).

17.3USB Control Endpoint Mode Registers

All USB devices are required to have a control endpoint 0 (EPA0 and EPB0) that is used to initialize and control each USB address. Endpoint 0 provides access to the device configuration information and allows generic USB status and control accesses. Endpoint 0 is bidirectional to both receive and transmit data. The other endpoints are unidirectional, but selectable by the user as IN or OUT endpoints.

The endpoint mode registers are cleared during reset. When USB Status And Control Register Bits [6,7] are set to [0,0] or [1,0], the endpoint zero EPA0 and EPB0 mode registers use the format shown in Figure 17-2.

USB Device Endpoint Zero Mode (A0, B0)

 

 

 

Addresses 0x12(A0) and 0x42(B0)

Bit #

7

6

5

4

3

2

1

0

Bit Name

Endpoint 0

Endpoint 0

Endpoint 0

ACK

Mode Bit 3

Mode Bit 2

Mode Bit 1

Mode Bit 0

 

SETUP

IN

OUT

 

 

 

 

 

 

Received

Received

Received

 

 

 

 

 

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset

0

0

0

0

0

0

0

0

Figure 17-2. USB Device Endpoint Zero Mode Registers

Bits[3..0]: Mode.

These sets the mode which control how the control endpoint responds to traffic. Bit 4: ACK.

This bit is set whenever the SIE engages in a transaction to the register’s endpoint that completes with an ACK packet. Bit 5: Endpoint 0 OUT Received.

1 = Token received is an OUT token. 0 = Token received is not an OUT token. This bit is set by the SIE to report the type of token received by the corresponding device address is an OUT token. The bit must be cleared by firmware as part of the USB processing.

Bit 6: Endpoint 0 IN Received.

1 = Token received is an IN token. 0 = Token received is not an IN token. This bit is set by the SIE to report the type of token received by the corresponding device address is an IN token. The bit must be cleared by firmware as part of the USB processing.

Bit 7: Endpoint 0 SETUP Received.

1 = Token received is a SETUP token. 0 = Token received is not a SETUP token. This bit is set ONLY by the SIE to report the type of token received by the corresponding device address is a SETUP token. Any write to this bit by the CPU will clear it (set it to 0). The bit is forced HIGH from the start of the data packet phase of the SETUP transaction until the start of the ACK packet returned by the SIE. The CPU should not clear this bit during this interval, and subsequently, until the CPU first does an IORD to this endpoint 0 mode register. The bit must be cleared by firmware as part of the USB processing.[4]

Note:

4.In 5-endpoint mode (USB Status And Control Register Bits [7,6] are set to [0,1] or [1,1]), Register 0x42 serves as non-control endpoint 3, and has the format for non-control endpoints shown in Figure 17-3.

Document #: 38-08002 Rev. *D

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Contents Cypress Semiconductor Corporation USB Hub with MicrocontrollerCY7C65113C 19.0 16.017.0 18.0List of Tables Features USB Functional OverviewGpio I2CLogic Block Diagram Top View CY7C65113C 28-pin Soic Pin ConfigurationsProduct Summary Tables Pin AssignmentsI/O Register Summary Operand Opcode Cycles Instruction Set SummaryInstruction Set Summary Mnemonic14-bit Program Counter Programming ModelKB -32 Prom ends here CY7C65113C Program Memory begins here8-bit Program Stack Pointer PSP 8-bit Accumulator a8-bit Temporary Register MOV A, Dspinit 8-bit Data Stack Pointer DSPAddress Modes Xtalin Power-on ResetClocking XtaloutWatchdog Reset Suspend ModePort 0 Data Address General-purpose I/O PortsPort 0,1 Low Isink Gpio Configuration Address Gpio Configuration PortPort 0 Interrupt Enable 10.0 12-bit Free-Running TimerGpio Interrupt Enable Ports 2C Configuration Address 11.0 I2C Configuration RegisterTimer LSB Address Timer MSB AddressACK 12.0 I2C-compatible ControllerI2C Data Address 2C Status and Control AddressContinue/Busy Write 1 to indicate ready for next transaction IRQ Processor Status and Control RegisterProcessor Status and Control Address 0xFF Interrupts Global Interrupt Enable Register AddressUSB Endpoint Interrupt Enable Address Interrupt Vectors Interrupt Controller Function DiagramInterrupt Latency USB Bus Reset InterruptTimer Interrupt 14.8 I2C Interrupt USB Endpoint InterruptsUSB Hub Interrupt Gpio InterruptACK/NAK/STALL USB OverviewUSB Serial Interface Engine SIE USB EnumerationHub Ports Connect Status Connecting/Disconnecting a USB DeviceUSB Hub Hub Downstream Ports Status and Control Hub Ports Enable Register AddressHub Ports Enable Register Enabling/Disabling a USB DeviceHub Ports SE0 Status Address 0x4F Hub Downstream Ports Control Register Address 0x4BHub Ports Force Low Hub Ports Suspend Address 0x4D Downstream Port Suspend and ResumeHub Ports Data Hub Ports Data RegisterUSB Status and Control Address 0x1F USB Upstream Port Status and ControlHub Ports Resume Address 0x4E USB Device Address Device A, B Addresses 0x10A and 0x40B USB Serial Interface Engine OperationUSB Device Addresses USB Device EndpointsSize Label Start Address USB Control Endpoint Mode RegistersUSB Device Endpoint Zero Mode A0, B0 Stall USB Non-control Endpoint Mode RegistersUSB Non-control Device Endpoint Mode USB Endpoint Counter RegistersUpdate Endpoint Mode/Count Registers Update and Locking MechanismSetup Data Set Update only if Fifo is WrittenData SetSetup OUT USB Mode TablesDtog Dval Count Dtog Dval Count Endpoint Ports Register SummaryLOW Absolute Maximum Ratings Sample SchematicUpstream/Downstream Port Electrical CharacteristicsParameter Description Conditions Min Max Unit General USB InterfaceParameter Description Min Max Unit Clock Source Switching Characteristics fOSC = 6.0 MHzUSB Full-speed Signaling10 Timer SignalsCY7C65113C-SXCT Package DiagramOrdering Information Ordering Code Prom Size Package Type Operating RangeREV ECN no Issue Date Orig. Description of ChangeDocument History