Cypress CY7C65113C USB Overview, USB Serial Interface Engine SIE, USB Enumeration, Ack/Nak/Stall

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CY7C65113C

3.In slave transmit mode, after the slave transmits a byte of data: The ACK bit indicates if the master that requested the byte acknowledged the byte. If more bytes are to be sent, firmware writes the next byte into the Data Register and then sets the Xmit MODE and Continue/Busy bits as required.

4.In master transmit mode, after the master sends a byte of data. Firmware should load the Data Register if necessary, and set the Xmit MODE, MSTR MODE, and Continue/Busy bits appropriately. Clearing the MSTR MODE bit issues a stop signal to the I2C-compatible bus and return to the idle state.

5.In master receive mode, after the master receives a byte of data: Firmware should read the data and set the ACK and Continue/Busy bits appropriately for the next byte. Clearing the MSTR MODE bit at the same time causes the master state machine to issue a stop signal to the I2C-compatible bus and leave the I2C-compatible hardware in the idle state.

6.When the master loses arbitration: This condition clears the MSTR MODE bit and sets the ARB Lost/Restart bit immediately and then waits for a stop signal on the I2C-compatible bus to generate the interrupt.

The Continue/Busy bit is cleared by hardware prior to interrupt conditions 1 to 4. Once the Data Register has been read or written, firmware should configure the other control bits and set the Continue/Busy bit for subsequent transactions. Following an interrupt from master mode, firmware should perform only one write to the Status and Control Register that sets the Continue/Busy bit, without checking the value of the Continue/Busy bit. The Busy bit may otherwise be active and I2C register contents may be changed by the hardware during the transaction, until the I2C interrupt occurs.

15.0USB Overview

The USB hardware includes a USB Hub repeater with one upstream and up to seven downstream ports. The USB Hub repeater interfaces to the microcontroller through a full-speed serial interface engine (SIE). An external series resistor of Rext must be placed in series with all upstream and downstream USB outputs in order to meet the USB driver requirements of the USB specification. The CY7C65113C microcontroller can provide the functionality of a compound device consisting of a USB hub and permanently attached functions.

15.1USB Serial Interface Engine (SIE)

The SIE allows the CY7C65113C microcontroller to communicate with the USB host through the USB repeater portion of the hub. The SIE simplifies the interface between the microcontroller and USB by incorporating hardware that handles the following USB bus activity independently of the microcontroller:

Bit stuffing/unstuffing

Checksum generation/checking

ACK/NAK/STALL

Token type identification

Address checking.

Firmware is required to handle the following USB interface tasks:

Coordinate enumeration by responding to SETUP packets

Fill and empty the FIFOs

Suspend/Resume coordination

Verify and select DATA toggle values.

15.2USB Enumeration

The internal hub and any compound device function are enumerated under firmware control. The hub is enumerated first, followed by any integrated compound function. After the hub is enumerated, the USB host can read hub connection status to determine which (if any) of the downstream ports need to be enumerated. The following is a brief summary of the typical enumeration process of the CY7C65113C by the USB host. For a detailed description of the enumeration process, refer to the USB specifi- cation.

In this description, ‘Firmware’ refers to embedded firmware in the CY7C65113C controller.

1.The host computer sends a SETUP packet followed by a DATA packet to USB address 0 requesting the Device descriptor.

2.Firmware decodes the request and retrieves its Device descriptor from the program memory tables.

3.The host computer performs a control read sequence and Firmware responds by sending the Device descriptor over the USB bus, via the on-chip FIFOs.

4.After receiving the descriptor, the host sends a SETUP packet followed by a DATA packet to address 0 assigning a new USB address to the device.

5.Firmware stores the new address in its USB Device Address Register (for example, as Address B) after the no-data control sequence completes.

Document #: 38-08002 Rev. *D

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Contents USB Hub with Microcontroller Cypress Semiconductor CorporationCY7C65113C 16.0 17.018.0 19.0List of Tables Features Functional Overview GpioI2C USBLogic Block Diagram Pin Configurations Product Summary TablesPin Assignments Top View CY7C65113C 28-pin SoicI/O Register Summary Instruction Set Summary Instruction Set SummaryMnemonic Operand Opcode CyclesProgramming Model 14-bit Program CounterProgram Memory begins here KB -32 Prom ends here CY7C65113C8-bit Temporary Register 8-bit Accumulator a8-bit Program Stack Pointer PSP Address Modes 8-bit Data Stack Pointer DSPMOV A, Dspinit Power-on Reset ClockingXtalout XtalinSuspend Mode Watchdog ResetPort 0,1 Low Isink General-purpose I/O PortsPort 0 Data Address Gpio Configuration Port Gpio Configuration AddressGpio Interrupt Enable Ports 10.0 12-bit Free-Running TimerPort 0 Interrupt Enable 11.0 I2C Configuration Register Timer LSB AddressTimer MSB Address 2C Configuration Address12.0 I2C-compatible Controller I2C Data Address2C Status and Control Address ACKContinue/Busy Write 1 to indicate ready for next transaction Processor Status and Control Address 0xFF Processor Status and Control RegisterIRQ USB Endpoint Interrupt Enable Address Global Interrupt Enable Register AddressInterrupts Interrupt Controller Function Diagram Interrupt VectorsTimer Interrupt USB Bus Reset InterruptInterrupt Latency USB Endpoint Interrupts USB Hub InterruptGpio Interrupt 14.8 I2C InterruptUSB Overview USB Serial Interface Engine SIEUSB Enumeration ACK/NAK/STALLUSB Hub Connecting/Disconnecting a USB DeviceHub Ports Connect Status Hub Ports Enable Register Address Hub Ports Enable RegisterEnabling/Disabling a USB Device Hub Downstream Ports Status and ControlHub Ports Force Low Hub Downstream Ports Control Register Address 0x4BHub Ports SE0 Status Address 0x4F Downstream Port Suspend and Resume Hub Ports DataHub Ports Data Register Hub Ports Suspend Address 0x4DHub Ports Resume Address 0x4E USB Upstream Port Status and ControlUSB Status and Control Address 0x1F USB Serial Interface Engine Operation USB Device AddressesUSB Device Endpoints USB Device Address Device A, B Addresses 0x10A and 0x40BUSB Device Endpoint Zero Mode A0, B0 USB Control Endpoint Mode RegistersSize Label Start Address USB Non-control Endpoint Mode Registers USB Non-control Device Endpoint ModeUSB Endpoint Counter Registers StallSetup Endpoint Mode/Count Registers Update and Locking MechanismUpdate Update only if Fifo is Written DataSet Data SetUSB Mode Tables Setup OUTDtog Dval Count Dtog Dval Count Endpoint Register Summary PortsLOW Sample Schematic Absolute Maximum RatingsElectrical Characteristics Parameter Description Conditions Min Max Unit GeneralUSB Interface Upstream/Downstream PortSwitching Characteristics fOSC = 6.0 MHz USB Full-speed Signaling10Timer Signals Parameter Description Min Max Unit Clock SourcePackage Diagram Ordering InformationOrdering Code Prom Size Package Type Operating Range CY7C65113C-SXCTDocument History Issue Date Orig. Description of ChangeREV ECN no