Cypress CY7C65113C manual Endpoint Mode/Count Registers Update and Locking Mechanism, Setup

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CY7C65113C

Bit 6: Data Valid.

This bit is set on receiving a proper CRC when the endpoint FIFO buffer is loaded with data during transactions. This bit is used OUT and SETUP tokens only. If the CRC is not correct, the endpoint interrupt occurs, but Data Valid is cleared to a zero.

Bit 7: Data 0/1 Toggle.

This bit selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. For IN transactions, firmware must set this bit to the desired state. For OUT or SETUP transactions, the hardware sets this bit to the state of the received Data Toggle bit.

Whenever the count updates from a SETUP or OUT transaction on endpoint 0, the counter register locks and cannot be written by the CPU. Reading the register unlocks it. This prevents firmware from overwriting a status update on incoming SETUP or OUT transactions before firmware has a chance to read the data. Only endpoint 0 counter register is locked when updated. The locking mechanism does not apply to the count registers of other endpoints.

17.6Endpoint Mode/Count Registers Update and Locking Mechanism

The contents of the endpoint mode and counter registers are updated, based on the packet flow diagram in Figure 17-5. Two time points, SETUP and UPDATE, are shown in the same figure. The following activities occur at each time point:

SETUP:

The SETUP bit of the endpoint 0 mode register is forced HIGH at this time. This bit is forced HIGH by the SIE until the end of the data phase of a control write transfer. The SETUP bit can not be cleared by firmware during this time.

The affected mode and counter registers of endpoint 0 are locked from any CPU writes once they are updated. These registers can be unlocked by a CPU read, only if the read operation occurs after the UPDATE. The firmware needs to perform a register read as a part of the endpoint ISR processing to unlock the effected registers. The locking mechanism on mode and counter registers ensures that the firmware recognizes the changes that the SIE might have made since the previous IO read of that register.

UPDATE:

1.Endpoint Mode Register – All the bits are updated (except the SETUP bit of the endpoint 0 mode register).

2.Counter Registers – All bits are updated.

3.Interrupt – If an interrupt is to be generated as a result of the transaction, the interrupt flag for the corresponding endpoint is set at this time. For details on what conditions are required to generate an endpoint interrupt, refer to Table 18-2.

4.The contents of the updated endpoint 0 mode and counter registers are locked, except the SETUP bit of the endpoint 0 mode register which was locked earlier.

Document #: 38-08002 Rev. *D

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Contents Cypress Semiconductor Corporation USB Hub with MicrocontrollerCY7C65113C 17.0 16.018.0 19.0List of Tables Features Gpio Functional OverviewI2C USBLogic Block Diagram Product Summary Tables Pin ConfigurationsPin Assignments Top View CY7C65113C 28-pin SoicI/O Register Summary Instruction Set Summary Instruction Set SummaryMnemonic Operand Opcode Cycles14-bit Program Counter Programming ModelKB -32 Prom ends here CY7C65113C Program Memory begins here8-bit Temporary Register 8-bit Accumulator a8-bit Program Stack Pointer PSP Address Modes 8-bit Data Stack Pointer DSPMOV A, Dspinit Clocking Power-on ResetXtalout XtalinWatchdog Reset Suspend ModePort 0,1 Low Isink General-purpose I/O PortsPort 0 Data Address Gpio Configuration Address Gpio Configuration PortGpio Interrupt Enable Ports 10.0 12-bit Free-Running TimerPort 0 Interrupt Enable Timer LSB Address 11.0 I2C Configuration RegisterTimer MSB Address 2C Configuration AddressI2C Data Address 12.0 I2C-compatible Controller2C Status and Control Address ACKContinue/Busy Write 1 to indicate ready for next transaction Processor Status and Control Address 0xFF Processor Status and Control RegisterIRQ USB Endpoint Interrupt Enable Address Global Interrupt Enable Register AddressInterrupts Interrupt Vectors Interrupt Controller Function DiagramTimer Interrupt USB Bus Reset InterruptInterrupt Latency USB Hub Interrupt USB Endpoint InterruptsGpio Interrupt 14.8 I2C InterruptUSB Serial Interface Engine SIE USB OverviewUSB Enumeration ACK/NAK/STALLUSB Hub Connecting/Disconnecting a USB DeviceHub Ports Connect Status Hub Ports Enable Register Hub Ports Enable Register AddressEnabling/Disabling a USB Device Hub Downstream Ports Status and ControlHub Ports Force Low Hub Downstream Ports Control Register Address 0x4BHub Ports SE0 Status Address 0x4F Hub Ports Data Downstream Port Suspend and ResumeHub Ports Data Register Hub Ports Suspend Address 0x4DHub Ports Resume Address 0x4E USB Upstream Port Status and ControlUSB Status and Control Address 0x1F USB Device Addresses USB Serial Interface Engine OperationUSB Device Endpoints USB Device Address Device A, B Addresses 0x10A and 0x40BUSB Device Endpoint Zero Mode A0, B0 USB Control Endpoint Mode RegistersSize Label Start Address USB Non-control Device Endpoint Mode USB Non-control Endpoint Mode RegistersUSB Endpoint Counter Registers StallSetup Endpoint Mode/Count Registers Update and Locking MechanismUpdate Data Update only if Fifo is WrittenSet Data SetSetup OUT USB Mode TablesDtog Dval Count Dtog Dval Count Endpoint Ports Register SummaryLOW Absolute Maximum Ratings Sample SchematicParameter Description Conditions Min Max Unit General Electrical CharacteristicsUSB Interface Upstream/Downstream PortUSB Full-speed Signaling10 Switching Characteristics fOSC = 6.0 MHzTimer Signals Parameter Description Min Max Unit Clock SourceOrdering Information Package DiagramOrdering Code Prom Size Package Type Operating Range CY7C65113C-SXCTDocument History Issue Date Orig. Description of ChangeREV ECN no