Cypress CY7C65113C manual Dtog Dval Count

Page 40

CY7C65113C

Comments

Some Mode Bits are automatically changed by the SIE in response to certain USB transactions. For example, if the Mode Bits [3:0] are set to '1111' which is ACK IN-Status OUT mode as shown in Table 18-1, the SIE will change the endpoint Mode Bits [3:0] to NAK IN-Status OUT mode (1110) after ACK’ing a valid status stage OUT token. The firmware needs to update the mode for the SIE to respond appropriately. See Table 18-1for more details on what modes will be changed by the SIE. A disabled endpoint will remain disabled until changed by firmware, and all endpoints reset to the disabled mode (0000). Firmware normally enables the endpoint mode after a SetConfiguration request.

Any SETUP packet to an enabled endpoint with mode set to accept SETUPs will be changed by the SIE to 0001 (NAKing INs and OUTs). Any mode set to accept a SETUP will send an ACK handshake to a valid SETUP token.

The control endpoint has three status bits for identifying the token type received (SETUP, IN, or OUT), but the endpoint must be placed in the correct mode to function as such. Non-control endpoints should not be placed into modes that accept SETUPs. Note that most modes that control transactions involving an ending ACK, are changed by the SIE to a corresponding mode which NAKs subsequent packets following the ACK. Exceptions are modes 1010 and 1110

.

Table 18-2. Decode table for Table 18-3: “Details of Modes for Differing Traffic Condition

Properties of Incoming

Changes to the Internal Register made by the SIE on receiving an incoming packet

Interrupt

Packets

from the host

3

2

1

0

Token

count

buffer

dval

DTOG

DVAL

COUNT

Setup

In

Out

ACK

3

2

1

0

Response

Int

 

 

 

 

 

 

 

 

 

 

 

 

Byte

 

Count (bits 0..5, Figure 17-4)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Endpoint

 

Mode

 

 

 

 

Data

 

Valid (bit 6, Figure 17-4)

 

 

SIE’s

 

Response

 

 

 

 

 

 

 

encoding

 

 

 

 

 

 

 

 

 

 

 

 

 

 

to the Host

 

 

 

Received

Token

 

 

Data0/1 (bit7 Figure 17-4)

 

 

 

 

 

 

 

 

 

 

(SETUP/IN/OUT)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PID Status Bits

 

 

Endpoint Mode bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(Bit[7..5], Figure 17-2)

 

Changed by the SIE

 

 

 

 

 

 

 

The validity of the received data

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The quality status of the DMA buffer

 

 

 

 

 

 

 

Legend:

 

 

The

number of received bytes

 

 

Acknowledge phase completed

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

TX : transmit

UC : unchanged

 

 

 

 

 

 

 

 

 

 

 

RX : receive

TX0 :Transmit 0 length packet

 

 

 

 

 

 

 

available for Control endpoint only x: don’t care

The response of the SIE can be summarized as follows:

1.The SIE will only respond to valid transactions, and will ignore non-valid ones.

2.The SIE will generate an interrupt when a valid transaction is completed or when the FIFO is corrupted. FIFO corruption occurs during an OUT or SETUP transaction to a valid internal address, that ends with a non-valid CRC.

3.An incoming Data packet is valid if the count is < Endpoint Size + 2 (includes CRC) and passes all error checking;

4.An IN will be ignored by an OUT configured endpoint and visa versa.

5.The IN and OUT PID status is updated at the end of a transaction.

6.The SETUP PID status is updated at the beginning of the Data packet phase.

7.The entire Endpoint 0 mode register and the Count register are locked to CPU writes at the end of any transaction to that endpoint in which an ACK is transferred. These registers are only unlocked by a CPU read of the register, which should be done by the firmware only after the transaction is complete. This represents about a 1-∝s window in which the CPU is locked from register writes to these USB registers. Normally the firmware should perform a register read at the beginning of the Endpoint ISRs to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction. Note that the setup bit of the mode register is NOT locked. This means that before writing to the mode register, firmware must first read the register to make sure that the setup bit is not set (which indicates a setup was received, while processing the current USB request). This read will of course unlock the register. So care must be taken not to overwrite the register elsewhere.

Document #: 38-08002 Rev. *D

Page 40 of 49

[+] Feedback

Page 39 Page 41
Image 40
Page 39 Page 41
Contents USB Hub with Microcontroller Cypress Semiconductor CorporationCY7C65113C 16.0 17.018.0 19.0List of Tables Features Functional Overview GpioI2C USBLogic Block Diagram Pin Configurations Product Summary TablesPin Assignments Top View CY7C65113C 28-pin SoicI/O Register Summary Instruction Set Summary Instruction Set SummaryMnemonic Operand Opcode CyclesProgramming Model 14-bit Program CounterProgram Memory begins here KB -32 Prom ends here CY7C65113C8-bit Temporary Register 8-bit Accumulator a8-bit Program Stack Pointer PSP Address Modes 8-bit Data Stack Pointer DSPMOV A, Dspinit Power-on Reset ClockingXtalout XtalinSuspend Mode Watchdog ResetPort 0,1 Low Isink General-purpose I/O PortsPort 0 Data Address Gpio Configuration Port Gpio Configuration AddressGpio Interrupt Enable Ports 10.0 12-bit Free-Running TimerPort 0 Interrupt Enable 11.0 I2C Configuration Register Timer LSB AddressTimer MSB Address 2C Configuration Address12.0 I2C-compatible Controller I2C Data Address2C Status and Control Address ACKContinue/Busy Write 1 to indicate ready for next transaction Processor Status and Control Address 0xFF Processor Status and Control RegisterIRQ USB Endpoint Interrupt Enable Address Global Interrupt Enable Register AddressInterrupts Interrupt Controller Function Diagram Interrupt VectorsTimer Interrupt USB Bus Reset InterruptInterrupt Latency USB Endpoint Interrupts USB Hub InterruptGpio Interrupt 14.8 I2C InterruptUSB Overview USB Serial Interface Engine SIEUSB Enumeration ACK/NAK/STALLUSB Hub Connecting/Disconnecting a USB DeviceHub Ports Connect Status Hub Ports Enable Register Address Hub Ports Enable RegisterEnabling/Disabling a USB Device Hub Downstream Ports Status and ControlHub Ports Force Low Hub Downstream Ports Control Register Address 0x4BHub Ports SE0 Status Address 0x4F Downstream Port Suspend and Resume Hub Ports DataHub Ports Data Register Hub Ports Suspend Address 0x4DHub Ports Resume Address 0x4E USB Upstream Port Status and ControlUSB Status and Control Address 0x1F USB Serial Interface Engine Operation USB Device AddressesUSB Device Endpoints USB Device Address Device A, B Addresses 0x10A and 0x40BUSB Device Endpoint Zero Mode A0, B0 USB Control Endpoint Mode RegistersSize Label Start Address USB Non-control Endpoint Mode Registers USB Non-control Device Endpoint ModeUSB Endpoint Counter Registers StallSetup Endpoint Mode/Count Registers Update and Locking MechanismUpdate Update only if Fifo is Written DataSet Data SetUSB Mode Tables Setup OUTDtog Dval Count Dtog Dval Count Endpoint Register Summary PortsLOW Sample Schematic Absolute Maximum RatingsElectrical Characteristics Parameter Description Conditions Min Max Unit GeneralUSB Interface Upstream/Downstream PortSwitching Characteristics fOSC = 6.0 MHz USB Full-speed Signaling10Timer Signals Parameter Description Min Max Unit Clock SourcePackage Diagram Ordering InformationOrdering Code Prom Size Package Type Operating Range CY7C65113C-SXCTDocument History Issue Date Orig. Description of ChangeREV ECN no
Top Page Image Contents