Cypress CY7C65113C manual Endpoint

Page 42

CY7C65113C

Table 18-3. Details of Modes for Differing Traffic Conditions (see Table 18-2for the decode legend) (continued)

0

0

1

0

Out

!=2

UC

valid

updates

1

updates

UC

UC

1

UC

0

0

1

1

Stall

yes

0

0

1

0

Out

> 10

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

0

Out

x

UC

invalid

UC

UC

UC

UC

1

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

0

1

0

In

x

UC

x

UC

UC

UC

UC

1

UC

UC

0

0

1

1

Stall

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUT

ENDPOINT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Properties of Incoming Packet

 

 

Changes made by SIE to Internal Registers and Mode Bits

 

 

 

 

 

 

Mode Bits

 

token

count

buffer

dval

DTOG

DVAL

COUNT

Setup

In

Out

ACK

Mode Bits

Response

Intr

Normal Out/erroneous In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

Out

<= 10

data

valid

updates

1

updates

UC

UC

1

1

1

0

0

0

ACK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

Out

> 10

junk

x

updates

updates

updates

UC

UC

1

UC

NoChange

ignore

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

Out

x

junk

invalid

updates

0

updates

UC

UC

1

UC

NoChange

ignore

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

1

In

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(STALL[6] = 0)

 

1

0

0

1

In

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

Stall

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(STALL[6] = 1)

 

NAK

 

Out/erroneous In

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

Out

<= 10

UC

valid

UC

UC

UC

UC

UC

1

UC

NoChange

NAK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

Out

> 10

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

Out

x

UC

invalid

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

0

0

0

In

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Isochronous endpoint (Out)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

0

1

Out

x

updates

updates

updates

updates

updates

UC

UC

1

1

NoChange

RX

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

0

1

In

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IN

ENDPOINT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Properties of Incoming Packet

 

 

Changes made by SIE to Internal Registers and Mode Bits

 

 

 

 

 

 

Mode Bits

 

token

count

buffer

dval

DTOG

DVAL

COUNT

Setup

In

Out

ACK

Mode Bits

Response

Intr

Normal In/erroneous

Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

0

1

Out

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(STALL[6] = 0)

 

1

1

0

1

Out

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

stall

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(STALL[6] = 1)

 

1

1

0

1

In

x

UC

x

UC

UC

UC

UC

1

UC

1

1

1

0

0

ACK (back)

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NAK

In/erroneous Out

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

0

0

Out

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

1

0

0

In

x

UC

x

UC

UC

UC

UC

1

UC

UC

NoChange

NAK

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Isochronous endpoint (In)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

1

Out

x

UC

x

UC

UC

UC

UC

UC

UC

UC

NoChange

ignore

no

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

1

1

1

In

x

UC

x

UC

UC

UC

UC

1

UC

UC

NoChange

TX

yes

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Document #: 38-08002 Rev. *D

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Contents USB Hub with Microcontroller Cypress Semiconductor CorporationCY7C65113C 18.0 16.017.0 19.0List of Tables Features I2C Functional OverviewGpio USBLogic Block Diagram Pin Assignments Pin ConfigurationsProduct Summary Tables Top View CY7C65113C 28-pin SoicI/O Register Summary Mnemonic Instruction Set SummaryInstruction Set Summary Operand Opcode CyclesProgramming Model 14-bit Program CounterProgram Memory begins here KB -32 Prom ends here CY7C65113C8-bit Accumulator a 8-bit Temporary Register8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP Address ModesMOV A, Dspinit Xtalout Power-on ResetClocking XtalinSuspend Mode Watchdog ResetGeneral-purpose I/O Ports Port 0,1 Low IsinkPort 0 Data Address Gpio Configuration Port Gpio Configuration Address10.0 12-bit Free-Running Timer Gpio Interrupt Enable PortsPort 0 Interrupt Enable Timer MSB Address 11.0 I2C Configuration RegisterTimer LSB Address 2C Configuration Address2C Status and Control Address 12.0 I2C-compatible ControllerI2C Data Address ACKContinue/Busy Write 1 to indicate ready for next transaction Processor Status and Control Register Processor Status and Control Address 0xFFIRQ Global Interrupt Enable Register Address USB Endpoint Interrupt Enable AddressInterrupts Interrupt Controller Function Diagram Interrupt VectorsUSB Bus Reset Interrupt Timer InterruptInterrupt Latency Gpio Interrupt USB Endpoint InterruptsUSB Hub Interrupt 14.8 I2C InterruptUSB Enumeration USB OverviewUSB Serial Interface Engine SIE ACK/NAK/STALLConnecting/Disconnecting a USB Device USB HubHub Ports Connect Status Enabling/Disabling a USB Device Hub Ports Enable Register AddressHub Ports Enable Register Hub Downstream Ports Status and ControlHub Downstream Ports Control Register Address 0x4B Hub Ports Force LowHub Ports SE0 Status Address 0x4F Hub Ports Data Register Downstream Port Suspend and ResumeHub Ports Data Hub Ports Suspend Address 0x4DUSB Upstream Port Status and Control Hub Ports Resume Address 0x4EUSB Status and Control Address 0x1F USB Device Endpoints USB Serial Interface Engine OperationUSB Device Addresses USB Device Address Device A, B Addresses 0x10A and 0x40BUSB Control Endpoint Mode Registers USB Device Endpoint Zero Mode A0, B0Size Label Start Address USB Endpoint Counter Registers USB Non-control Endpoint Mode RegistersUSB Non-control Device Endpoint Mode StallEndpoint Mode/Count Registers Update and Locking Mechanism SetupUpdate Set Update only if Fifo is WrittenData Data SetUSB Mode Tables Setup OUTDtog Dval Count Dtog Dval Count Endpoint Register Summary PortsLOW Sample Schematic Absolute Maximum RatingsUSB Interface Electrical CharacteristicsParameter Description Conditions Min Max Unit General Upstream/Downstream PortTimer Signals Switching Characteristics fOSC = 6.0 MHzUSB Full-speed Signaling10 Parameter Description Min Max Unit Clock SourceOrdering Code Prom Size Package Type Operating Range Package DiagramOrdering Information CY7C65113C-SXCTIssue Date Orig. Description of Change Document HistoryREV ECN no
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