Cypress CY7C65113C manual 10.0 12-bit Free-Running Timer, Gpio Interrupt Enable Ports

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CY7C65113C

 

 

 

 

 

 

 

 

 

 

 

Table 9-1. GPIO Port Output Control Truth Table and Interrupt Polarity

 

 

 

 

 

 

 

 

 

 

Port Config Bit 1

Port Config Bit 0

Data Register

Output Drive Strength

Interrupt Enable Bit

Interrupt Polarity

 

 

 

 

 

 

 

 

 

 

1

 

1

 

0

Output LOW

0

Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Resistive

1

– (Falling Edge)

 

 

 

 

 

 

 

 

 

 

1

 

0

 

0

Output LOW

0

Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Output HIGH

1

Disabled

 

 

 

 

 

 

 

 

 

 

0

 

1

 

0

Output LOW

0

Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Hi-Z

1

– (Falling Edge)

 

 

 

 

 

 

 

 

 

 

0

 

0

 

0

Output LOW

0

Disabled

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

Hi-Z

1

+ (Rising Edge)

 

 

 

 

 

 

 

 

 

 

 

Q1, Q2, and Q3 discussed below are the transistors referenced in Figure 9-1. The available GPIO drive strength are:

Output LOW Mode: The pin’s Data Register is set to ‘0.’

Writing ‘0’ to the pin’s Data Register puts the pin in output LOW mode, regardless of the contents of the Port Configuration Bits[1:0]. In this mode, Q1 and Q2 are OFF. Q3 is ON. The GPIO pin is driven LOW through Q3.

Output HIGH Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘10.’

In this mode, Q1 and Q3 are OFF. Q2 is ON. The GPIO is pulled up through Q2. The GPIO pin is capable of sourcing... of current.

Resistive Mode: The pin’s Data Register is set to 1 and the Port Configuration Bits[1:0] is set to ‘11.’

Q2 and Q3 are OFF. Q1 is ON. The GPIO pin is pulled up with an internal 14kresistor. In resistive mode, the pin may serve as an input. Reading the pin’s Data Register returns a logic HIGH if the pin is not driven LOW by an external source.

Hi-Z Mode: The pin’s Data Register is set to1 and Port Configuration Bits[1:0] is set either ‘00’ or ‘01.’

Q1, Q2, and Q3 are all OFF. The GPIO pin is not driven internally. In this mode, the pin may serve as an input. Reading the Port Data Register returns the actual logic value on the port pins.

9.2GPIO Interrupt Enable Ports

Each GPIO pin can be individually enabled or disabled as an interrupt source. The Port 0–1 Interrupt Enable Registers provide this feature with an Interrupt Enable bit for each GPIO pin.

During a reset, GPIO interrupts are disabled by clearing all of the GPIO Interrupt Enable bits. Writing a ‘1’ to a GPIO Interrupt Enable bit enables GPIO interrupts from the corresponding input pin. All GPIO pins share a common interrupt, as discussed in Section 14.7.

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Address 0x04

Port 0 Interrupt Enable

 

 

 

 

 

 

 

Bit #

7

6

 

5

4

3

2

1

 

0

Bit Name

P0.7 Intr

P0.6

Intr

P0.5 Intr

P0.4 Intr

P0.3 Intr

P0.2 Intr

P0.1 Intr

 

P0.0 Intr

 

Enable

Enable

Enable

Enable

Enable

Enable

Enable

 

Enable

Read/Write

W

W

W

W

W

W

W

 

W

Reset

0

0

 

0

0

0

0

0

 

0

 

 

 

 

Figure 9-5. Port 0 Interrupt Enable

 

 

 

 

Port 1 Interrupt Enable

 

 

 

 

 

 

 

Address 0x05

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

 

5

4

3

2

1

 

0

Bit Name

Reserved

Reserved

Reserved

Reserved

Reserved

P0.2 Intr

P1.1 Intr

 

P1.0 Intr

 

 

 

 

 

 

 

Enable

Enable

 

Enable

Read/Write

-

-

 

-

-

-

W

W

 

W

Reset

-

-

 

-

-

-

0

0

 

0

Figure 9-6. Port 1 Interrupt Enable

10.012-bit Free-Running Timer

The 12-bit timer operates with a 1-s tick, provides two interrupts (128 s and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower eight bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually reading the count stored in the temporary register. The effect of this is to ensure a stable 12-bit timer value can be read, even when the two reads are separated in time.

Document #: 38-08002 Rev. *D

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Contents Cypress Semiconductor Corporation USB Hub with MicrocontrollerCY7C65113C 19.0 16.017.0 18.0List of Tables Features USB Functional OverviewGpio I2CLogic Block Diagram Top View CY7C65113C 28-pin Soic Pin ConfigurationsProduct Summary Tables Pin AssignmentsI/O Register Summary Operand Opcode Cycles Instruction Set SummaryInstruction Set Summary Mnemonic14-bit Program Counter Programming ModelKB -32 Prom ends here CY7C65113C Program Memory begins here8-bit Temporary Register 8-bit Accumulator a8-bit Program Stack Pointer PSP Address Modes 8-bit Data Stack Pointer DSPMOV A, Dspinit Xtalin Power-on ResetClocking XtaloutWatchdog Reset Suspend ModePort 0,1 Low Isink General-purpose I/O PortsPort 0 Data Address Gpio Configuration Address Gpio Configuration PortGpio Interrupt Enable Ports 10.0 12-bit Free-Running TimerPort 0 Interrupt Enable 2C Configuration Address 11.0 I2C Configuration RegisterTimer LSB Address Timer MSB AddressACK 12.0 I2C-compatible ControllerI2C Data Address 2C Status and Control AddressContinue/Busy Write 1 to indicate ready for next transaction Processor Status and Control Address 0xFF Processor Status and Control RegisterIRQ USB Endpoint Interrupt Enable Address Global Interrupt Enable Register AddressInterrupts Interrupt Vectors Interrupt Controller Function DiagramTimer Interrupt USB Bus Reset InterruptInterrupt Latency 14.8 I2C Interrupt USB Endpoint InterruptsUSB Hub Interrupt Gpio InterruptACK/NAK/STALL USB OverviewUSB Serial Interface Engine SIE USB EnumerationUSB Hub Connecting/Disconnecting a USB DeviceHub Ports Connect Status Hub Downstream Ports Status and Control Hub Ports Enable Register AddressHub Ports Enable Register Enabling/Disabling a USB DeviceHub Ports Force Low Hub Downstream Ports Control Register Address 0x4BHub Ports SE0 Status Address 0x4F Hub Ports Suspend Address 0x4D Downstream Port Suspend and ResumeHub Ports Data Hub Ports Data RegisterHub Ports Resume Address 0x4E USB Upstream Port Status and ControlUSB Status and Control Address 0x1F USB Device Address Device A, B Addresses 0x10A and 0x40B USB Serial Interface Engine OperationUSB Device Addresses USB Device EndpointsUSB Device Endpoint Zero Mode A0, B0 USB Control Endpoint Mode RegistersSize Label Start Address Stall USB Non-control Endpoint Mode RegistersUSB Non-control Device Endpoint Mode USB Endpoint Counter RegistersSetup Endpoint Mode/Count Registers Update and Locking MechanismUpdate Data Set Update only if Fifo is WrittenData SetSetup OUT USB Mode TablesDtog Dval Count Dtog Dval Count Endpoint Ports Register SummaryLOW Absolute Maximum Ratings Sample SchematicUpstream/Downstream Port Electrical CharacteristicsParameter Description Conditions Min Max Unit General USB InterfaceParameter Description Min Max Unit Clock Source Switching Characteristics fOSC = 6.0 MHzUSB Full-speed Signaling10 Timer SignalsCY7C65113C-SXCT Package DiagramOrdering Information Ordering Code Prom Size Package Type Operating RangeDocument History Issue Date Orig. Description of ChangeREV ECN no