Cypress CY7C65113C manual Programming Model, bit Program Counter

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CY7C65113C

Table 4-3. Instruction Set Summary (continued)

MNEMONIC

operand

opcode

cycles

XPAGE

 

1F

4

 

 

 

 

MOV A,X

 

40

4

 

 

 

 

MOV X,A

 

41

4

 

 

 

 

MOV PSP,A

 

60

4

 

 

 

 

CALL

addr

50-5F

10

 

 

 

 

JMP

addr

80-8F

5

 

 

 

 

CALL

addr

90-9F

10

 

 

 

 

JZ

addr

A0-AF

5 (or 4)

 

 

 

 

JNZ

addr

B0-BF

5 (or 4)

 

 

 

 

MNEMONIC

operand

opcode

cycles

RET

 

3F

8

 

 

 

 

DI

 

70

4

 

 

 

 

EI

 

72

4

 

 

 

 

RETI

 

73

8

 

 

 

 

JC

addr

C0-CF

5 (or 4)

 

 

 

 

JNC

addr

D0-DF

5 (or 4)

 

 

 

 

JACC

addr

E0-EF

7

 

 

 

 

INDEX

addr

F0-FF

14

 

 

 

 

 

 

 

 

5.0Programming Model

5.114-bit Program Counter

The 14-bit Program Counter (PC) allows access to up to 8 KB of PROM available with the CY7C65113C architecture. The top 32 bytes of the ROM in the 8K part are reserved for testing purposes. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000h. Typically, this is a jump instruction to a reset handler that initializes the application (see Interrupt Vectors on page 25).

The lower eight bits of the program counter are incremented as instructions are loaded and executed. The upper six bits of the program counter are incremented by executing an XPAGE instruction. As a result, the last instruction executed within a 256-byte “page” of sequential code should be an XPAGE instruction. The assembler directive “XPAGEON” causes the assembler to insert XPAGE instructions automatically. Because instructions can be either one or two bytes long, the assembler may occasionally need to insert a NOP followed by an XPAGE to execute correctly.

The address of the next instruction to be executed, the carry flag, and the zero flag are saved as two bytes on the program stack during an interrupt acknowledge or a CALL instruction. The program counter, carry flag, and zero flag are restored from the program stack during a RETI instruction. Only the program counter is restored during a RET instruction.

The program counter cannot be accessed directly by the firmware. The program stack can be examined by reading SRAM from location 0x00 and up.

Document #: 38-08002 Rev. *D

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Contents Cypress Semiconductor Corporation USB Hub with MicrocontrollerCY7C65113C 19.0 16.017.0 18.0List of Tables Features USB Functional OverviewGpio I2CLogic Block Diagram Top View CY7C65113C 28-pin Soic Pin ConfigurationsProduct Summary Tables Pin AssignmentsI/O Register Summary Operand Opcode Cycles Instruction Set SummaryInstruction Set Summary Mnemonic14-bit Program Counter Programming ModelKB -32 Prom ends here CY7C65113C Program Memory begins here8-bit Program Stack Pointer PSP 8-bit Accumulator a8-bit Temporary Register MOV A, Dspinit 8-bit Data Stack Pointer DSPAddress Modes Xtalin Power-on ResetClocking XtaloutWatchdog Reset Suspend ModePort 0 Data Address General-purpose I/O PortsPort 0,1 Low Isink Gpio Configuration Address Gpio Configuration PortPort 0 Interrupt Enable 10.0 12-bit Free-Running TimerGpio Interrupt Enable Ports 2C Configuration Address 11.0 I2C Configuration RegisterTimer LSB Address Timer MSB AddressACK 12.0 I2C-compatible ControllerI2C Data Address 2C Status and Control AddressContinue/Busy Write 1 to indicate ready for next transaction IRQ Processor Status and Control RegisterProcessor Status and Control Address 0xFF Interrupts Global Interrupt Enable Register AddressUSB Endpoint Interrupt Enable Address Interrupt Vectors Interrupt Controller Function DiagramInterrupt Latency USB Bus Reset InterruptTimer Interrupt 14.8 I2C Interrupt USB Endpoint InterruptsUSB Hub Interrupt Gpio InterruptACK/NAK/STALL USB OverviewUSB Serial Interface Engine SIE USB EnumerationHub Ports Connect Status Connecting/Disconnecting a USB DeviceUSB Hub Hub Downstream Ports Status and Control Hub Ports Enable Register AddressHub Ports Enable Register Enabling/Disabling a USB DeviceHub Ports SE0 Status Address 0x4F Hub Downstream Ports Control Register Address 0x4BHub Ports Force Low Hub Ports Suspend Address 0x4D Downstream Port Suspend and ResumeHub Ports Data Hub Ports Data RegisterUSB Status and Control Address 0x1F USB Upstream Port Status and ControlHub Ports Resume Address 0x4E USB Device Address Device A, B Addresses 0x10A and 0x40B USB Serial Interface Engine OperationUSB Device Addresses USB Device EndpointsSize Label Start Address USB Control Endpoint Mode RegistersUSB Device Endpoint Zero Mode A0, B0 Stall USB Non-control Endpoint Mode RegistersUSB Non-control Device Endpoint Mode USB Endpoint Counter RegistersUpdate Endpoint Mode/Count Registers Update and Locking MechanismSetup Data Set Update only if Fifo is WrittenData SetSetup OUT USB Mode TablesDtog Dval Count Dtog Dval Count Endpoint Ports Register SummaryLOW Absolute Maximum Ratings Sample SchematicUpstream/Downstream Port Electrical CharacteristicsParameter Description Conditions Min Max Unit General USB InterfaceParameter Description Min Max Unit Clock Source Switching Characteristics fOSC = 6.0 MHzUSB Full-speed Signaling10 Timer SignalsCY7C65113C-SXCT Package DiagramOrdering Information Ordering Code Prom Size Package Type Operating RangeREV ECN no Issue Date Orig. Description of ChangeDocument History