Cypress CY7C65113C manual Logic Block Diagram

					CY7C65113C
Logic Block Diagram
6-MHz crystal				USB	D+[0] Upstream
				Transceiver	D–[0]USB Port
PLL					Downstream USB Ports
					USB	D+[1]
48 MHz					Transceiver	D–[1]
Clock	12-MHz				USB
Divider						D+[2]
	8-bit
					Transceiver	D–[2]
	CPU
12 MHz			USB	Repeater
	PROM		SIE		USB	D+[3]
	8 KB				Transceiver	D–[3]
	RAM	Bus	Interrupt		USB	D+[4]
		-bit
	256 byte		Controller		Transceiver	D–[4]
		8
6 MHz	12-bit				Power management under firmware
	Timer				control using GPIO pins
				P0[0]
			GPIO
			PORT 0	P0[7]
	Watchdog			P1[0]
	Timer		GPIO
			PORT 1	P1[2]
	Power-on
	Reset
			I2C comp.	SCLK
			Interface	SDATA
			*I2C-compatible interface enabled by firmware through
			P1[1:0]
Document #: 38-08002 Rev. *D						Page 7 of 49

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