Cypress CY7C65113C manual Gpio Configuration Port, Gpio Configuration Address

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CY7C65113C

9.1GPIO Configuration Port

Every GPIO port can be programmed as inputs with internal pull-ups, outputs LOW or HIGH, or Hi-Z (floating, the pin is not driven internally). In addition, the interrupt polarity for each port can be programmed. The Port Configuration bits (Figure 9-4) and the Interrupt Enable bit (Figure 9-5through Figure 9-6) determine the interrupt polarity of the port pins

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GPIO Configuration

 

 

 

 

 

Address 0x08

Bit #

7

6

5

4

3

2

1

0

Bit Name

Reserved

Reserved

Reserved

Reserved

Port 1

Port 1

Port 0

Port 0

 

 

 

 

 

Config Bit 1

Config Bit 0

Config Bit 1

Config Bit 0

Read/Write

-

-

-

-

R/W

R/W

R/W

R/W

Reset

-

-

-

-

0

0

0

0

Figure 9-4. GPIO Configuration Register

As shown in Table 9-1below, a positive polarity on an input pin represents a rising edge interrupt (LOW to HIGH), and a negative polarity on an input pin represents a falling edge interrupt (HIGH to LOW).

The GPIO interrupt is generated when all of the following conditions are met: the Interrupt Enable bit of the associated Port Interrupt Enable Register is enabled, the GPIO Interrupt Enable bit of the Global Interrupt Enable Register (Figure 14-1) is enabled, the Interrupt Enable Sense (bit 2, Figure 13-1) is set, and the GPIO pin of the port sees an event matching the interrupt polarity.

The driving state of each GPIO pin is determined by the value written to the pin’s Data Register (Figure 9-2through Figure 9-3) and by its associated Port Configuration bits as shown in the GPIO Configuration Register (Figure 9-4). These ports are configured on a per-port basis, so all pins in a given port are configured together. The possible port configurations are detailed in Table 9-1. As shown in this table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled.

During reset, all of the bits in the GPIO Configuration Register are written with ‘0’ to select Hi-Z mode for all GPIO ports as the default configuration.

Document #: 38-08002 Rev. *D

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Contents USB Hub with Microcontroller Cypress Semiconductor CorporationCY7C65113C 18.0 16.017.0 19.0List of Tables Features I2C Functional OverviewGpio USBLogic Block Diagram Pin Assignments Pin ConfigurationsProduct Summary Tables Top View CY7C65113C 28-pin SoicI/O Register Summary Mnemonic Instruction Set SummaryInstruction Set Summary Operand Opcode CyclesProgramming Model 14-bit Program CounterProgram Memory begins here KB -32 Prom ends here CY7C65113C8-bit Accumulator a 8-bit Temporary Register8-bit Program Stack Pointer PSP 8-bit Data Stack Pointer DSP Address ModesMOV A, Dspinit Xtalout Power-on ResetClocking XtalinSuspend Mode Watchdog ResetGeneral-purpose I/O Ports Port 0,1 Low IsinkPort 0 Data Address Gpio Configuration Port Gpio Configuration Address10.0 12-bit Free-Running Timer Gpio Interrupt Enable PortsPort 0 Interrupt Enable Timer MSB Address 11.0 I2C Configuration RegisterTimer LSB Address 2C Configuration Address2C Status and Control Address 12.0 I2C-compatible ControllerI2C Data Address ACKContinue/Busy Write 1 to indicate ready for next transaction Processor Status and Control Register Processor Status and Control Address 0xFFIRQ Global Interrupt Enable Register Address USB Endpoint Interrupt Enable AddressInterrupts Interrupt Controller Function Diagram Interrupt VectorsUSB Bus Reset Interrupt Timer InterruptInterrupt Latency Gpio Interrupt USB Endpoint InterruptsUSB Hub Interrupt 14.8 I2C InterruptUSB Enumeration USB OverviewUSB Serial Interface Engine SIE ACK/NAK/STALLConnecting/Disconnecting a USB Device USB HubHub Ports Connect Status Enabling/Disabling a USB Device Hub Ports Enable Register AddressHub Ports Enable Register Hub Downstream Ports Status and ControlHub Downstream Ports Control Register Address 0x4B Hub Ports Force LowHub Ports SE0 Status Address 0x4F Hub Ports Data Register Downstream Port Suspend and ResumeHub Ports Data Hub Ports Suspend Address 0x4DUSB Upstream Port Status and Control Hub Ports Resume Address 0x4EUSB Status and Control Address 0x1F USB Device Endpoints USB Serial Interface Engine OperationUSB Device Addresses USB Device Address Device A, B Addresses 0x10A and 0x40BUSB Control Endpoint Mode Registers USB Device Endpoint Zero Mode A0, B0Size Label Start Address USB Endpoint Counter Registers USB Non-control Endpoint Mode RegistersUSB Non-control Device Endpoint Mode StallEndpoint Mode/Count Registers Update and Locking Mechanism SetupUpdate Set Update only if Fifo is WrittenData Data SetUSB Mode Tables Setup OUTDtog Dval Count Dtog Dval Count Endpoint Register Summary PortsLOW Sample Schematic Absolute Maximum RatingsUSB Interface Electrical CharacteristicsParameter Description Conditions Min Max Unit General Upstream/Downstream PortTimer Signals Switching Characteristics fOSC = 6.0 MHzUSB Full-speed Signaling10 Parameter Description Min Max Unit Clock SourceOrdering Code Prom Size Package Type Operating Range Package DiagramOrdering Information CY7C65113C-SXCTIssue Date Orig. Description of Change Document HistoryREV ECN no