Samsung spinpoint v40, 3.5" hard disk drives manual Host Interface Control Block

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DISK DRIVE OPERATION

5.2.2.1The Host Interface Control Block

The SID2001 AT Controller provides an ATA interface to the host computer and can attach to an ATA-1, 2,3,4 or ATA-5 host. It provides a means for the host to access the Task File registers used to control the transfer of data between host memory and the disk.

The Host Interface Control block can be programmed to execute various host read/write commands either completely automatically without any DSP intervention, semi-automatically with minimal DSP intervention, or manually with the aid of the DSP.

Of particular interest to most designers are the significant advances in ATA automation, which have been incorporated into the AT controller of SID2001. The highlights of ATA automation are:

•Automatic data transfer management for multi-sector Read/Write commands without DSP intervention.

•Automatic data transfer management for Read/Write Multiple commands without DSP intervention.

•Automatic execution of read commands (Auto-Read command execution) for cached data in the buffer by matching the first sector.

•Auto-Write command execution (first sector of a multiple sector write operation is automated, or the transfer of one sector of the selected single sector write operation is automated).

•Automatic Task File registers updates during automatic multi-sector transfers.

•Programmable methods of IRQ assertion allow automation to work with different BIOS implementations and different device drivers.

•Capability to execute multiple consecutive Auto-Write commands without loss of data in the buffer.

•96-byte host FIFO to allow automation to occur smoothly during discontinuities in transfers on the ATA interface.

•Ability to pause the ATA automatic transfers between the host and buffer on sector and block boundaries.

•Automation of an extensive portion of the ATA command set.

The SID2001 also supports a basic ATAPI reset command.

The SID2001 supports both PIO and DMA type transfers. The supported DMA type transfers include multi- word, and synchronous DMA transfers. DMA transfers and PIO transfers utilize the bus in 8- or 16-bit mode, depending upon the command being executed. The bus is automatically switched between 16- and 8-bit mode while performing Read Long and Write Long commands at the time of ECC byte transfers.

Additional functionality is provided in the Host Interface Control block by the following features:

•Programmable transfer length for automatic ECC byte transfer on the AT bus.

•Automatically inserted wait states are provided to support the IOCHRDY signal pin functions at any ATA interface speed.

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SpinPoint V40 Product Manual

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Contents Spinpoint SpinPoint V40 Product Manual Table of Contents Ervo S Ystem EAD and W Rite O Perations Irmware F EaturesSmart Programming Requirements Protocol OverviewTiming Maintenance Precautions Service and Repair107 General InformationTable of Figures Page User Definition Manual OrganizationScope Commands and Messages Terminology and ConventionsComputer Message Format C/SReference Key Features IntroductionDescription Standards and Regulations Hardware RequirementsSpecification Summary SpecificationsPhysical Specifications Logical ConfigurationsPerformance Specifications Power Requirements 28.71Environmental Specifications SV6003H SV6014H SV8004HReliability Specifications Mtbf POHInstallation Space RequirementsUnpacking Instructions MountingOrientation 2Mounting Dimensions in Millimeters Clearance 3Mounting-Screw ClearanceCable Connectors DC Power ConnectorAT-Bus Interface Connector VentilationSpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration Drive Installation 7DC Power Connector and AT-Bus Interface Cable ConnectionsSystem Startup Procedure ParameterSystem Setup Head / Disk Assembly HDA Base Casting AssemblyDC Spindle Motor Assembly Disk Drive OperationExploded Mechanical View Disk Stack Assembly Head Stack AssemblyVoice Coil Motor and Actuator Latch Assemblies Air Filtration SystemDigital Signal Process and Interface Controller Drive ElectronicsAT Disk Controller 2SID2001 AT Controller Block Diagram Host Interface Control Block Buffer Control Block Disk Control BlockSpinPoint V40 Product Manual Power Management Read/Write ICDisk ECC Control Block Frequency SynthesizerTime Base Generator Automatic Gain ControlAsymmetry Correction Circuitry ASC Analog Anti-Aliasing Low Pass Filter3Read/Write 88C5200 Servo System Read and Write OperationsRead Channel Firmware Features Write ChannelRead Caching Write Caching Defect Management Automatic Defect AllocationMulti-burst ECC Correction SmartBlank Signal Conventions Signal SummaryPhysical Interface Signal Descriptions DMACK- DMA Acknowledge Dmarq DMA RequestIntrq Drive Interrupt IOCS16- Drive 16-bit I/OPDIAG- Passed Diagnostics RESET- Drive ResetIordy I/O Channel Ready SD8 SD6 SD9 SD5 SD4SD3 SD2Drive Drive HostDIR Logical Interface GeneralBit Conventions EnvironmentSpinPoint V40 Product Manual Command Block Registers 2 I/O Register AddressControl Block Registers N N N A a aControl Block Register Descriptions Alternate Status Register 3F6hDrive Address Register 3F7h Device Control Register 3F6hCommand Block Register Descriptions Features Register 1F1hError Register 1F1h Data Register 1F0hCommand Register 1F7h Sector Count Register 1F2hCylinder High Register 1F5h Cylinder Low Register 1F4hStatus Register 1F7h BSY Drdy DWF DSC DRQ Corr IDX ERRAt Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Check Power Mode 98h, E5h Execute Device Diagnostics 90hDownload Micro Code 92h Flush Cache E7h Format Track 50hIdentify Device ECh Word Content Description XxxxCapabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Idle 97h,E3h Idle Immediate 95h,E1hInitialize Device Parameters 91h Read Buffer E4h Read Long 22hwith retry, 23h without retryRead Multiple Command C4h Read Native Max Address F8h Read Sectors 20hwith retry, 21hwithout retryRead Verify Sectors 40hwith retry, 41hwithout retry Recalibrate 1xhSeek 7xh Set Features EFh ModeInputs LBANormal outputs BSY Drdy DRQ ERRDescription Set Multiple Mode C6h Sleep 99h, E6hSmart disable operation D9h Standby 96h,E2hSmart B0h Smart enable/disable attribute autosave D2h Smart enable operations D8hSmart execute off-line immediate D4h Smart read data D0h Byte DescriptionsValue Definition Off-line data collection capabilitySmart capability Smart read log sector D5hSmart return status DAh Smart save attribution value D3hStandby 96h, E2h Standby Immediate 94h, E0hWrite Buffer E8h Write DMA CAhWrite Multiple Command C5h Write Sectors 30hwith retry, 31hwithout retrySpinPoint V40 Product Manual Reset Response Error PostingProgramming Requirements Command Error Register Status Register BBKPower Conditions Sleep modeStandby mode Idle modeNormal mode PIO Data in Commands Protocol OverviewPIO Data Out Commands PIO Read CommandPIO Read Aborted Command PIO Write Command PIO Write Aborted CommandBSY=0 DRDY=1 BSY=1 BSY=0 DRQ=1 BSY=1 DRQ=0Non-Data Commands DMA Data Transfer Commands Aborted DMA Command Initialize DMA Reset DMA Status BSY=0 BSY=1BSY=1 BSY=0 Timing Register transfersDIOR-/DIOW Write PIO timing parameters Mode PIO data transfersAddr valid See note T1 t2 DIOR-/DIOW Multiword DMA data transfer DIOR-/DIOWMultiword DMA timing parameters Mode Ultra DMA data transfer Initiating an Ultra DMA data in burstUltra DMA data burst timing requirements 19Ultra DMA data burst timing requirementsSustained Ultra DMA data in burst 5Sustained Ultra DMA data in burstHost pausing an Ultra DMA data in burst 6Host pausing an Ultra DMA data in burstDevice terminating an Ultra DMA data in burst 7Device terminating an Ultra DMA data in burst 100Host terminating an Ultra DMA data in burst 8Host terminating an Ultra DMA data in burstInitiating an Ultra DMA data out burst 9Initiating an Ultra DMA data out burst 102Sustained Ultra DMA data out burst 10Sustained Ultra DMA data out burstDevice pausing an Ultra DMA data out burst 11Device pausing an Ultra DMA data out burst 104Host terminating an Ultra DMA data out burst 12Host terminating an Ultra DMA data out burstDevice terminating an Ultra DMA data out burst 13Device terminating an Ultra DMA data out burst 106Maintenance Precautions Service And RepairGeneral Information
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