Samsung 3.5" hard disk drives Control Block Register Descriptions, Alternate Status Register 3F6h

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DISK DRIVE OPERATION

6.3.3 Control Block Register Descriptions

6.3.3.1Alternate Status Register (3F6h)

This register contains the same information as the Status register in the Command Block register. The only difference is that reading this register does not imply interrupt acknowledgment nor does it clear a pending interrupt.

7	6	5	4	3	2	1	0
BSY	DRDY	DWF	BSY	DRQ	CORR	IDX	ERR

NOTE: See section 6.3.4.10 for definitions of the bits in this register.

6.3.3.2Drive Address Register (3F7h)

This register contains the inverted drive select and head select addresses of the currently selected drive. The bits in this register are as follows:

7	6	5	4	3	2	1	0
HiZ	nWTG	nHS3	nHS2	nHS1	nHS0	nDS1	nDS0

•HiZ is always in a high impedance state.

•nWTG is the Write Gate bit. When writing to the disk drive is in progress, nWTG=0.

•nHS3 through nHS0 are the one's complement of the binary coded address of the currently selected head. For example, if nHS3 through nHS0 are 1100b, respectively, then head 3 is selected. nHS3 is the most significant bit.

•nDS1 is the drive select bit for drive 1. When drive 1 is selected and active, nDS1=0.

•nDS0 is the drive select bit for drive 0. When drive 0 is selected and active, nDS0=0.

NOTE: Caching, translation and master/slave may cause this register to contain invalid data.

6.3.3.3Device Control Register (3F6h)

The bits in this register are as follows:
7		6	5	4	3	2	1	0
	X	X	X	X	1	SRST	nIEN	0

•SRST is the host software reset bit. The drive is held reset when this bit is set. If two disk drives are daisy chained on the interface, this bit resets both simultaneously.

•nIEN is the enable bit for the drive interrupt to the host. When nIEN=0, and the drive is selected, INTRQ is enabled through a tri-state buffer. When nIEN=1, or the drive is not selected, the INTRQ signal is in a high impedance state.

SpinPoint V40 Product Manual

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Contents Spinpoint SpinPoint V40 Product Manual Table of Contents Ervo S Ystem EAD and W Rite O Perations Irmware F EaturesSmart Programming Requirements Protocol OverviewTiming Service and Repair Maintenance Precautions107 General InformationTable of Figures Page User Definition Manual OrganizationScope Terminology and Conventions Commands and MessagesComputer Message Format C/SReference Key Features IntroductionDescription Hardware Requirements Standards and RegulationsSpecifications Specification SummaryLogical Configurations Physical SpecificationsPerformance Specifications 28.71 Power RequirementsSV6003H SV6014H SV8004H Environmental SpecificationsMtbf POH Reliability SpecificationsSpace Requirements InstallationUnpacking Instructions MountingOrientation 2Mounting Dimensions in Millimeters 3Mounting-Screw Clearance ClearanceDC Power Connector Cable ConnectorsAT-Bus Interface Connector VentilationSpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration 7DC Power Connector and AT-Bus Interface Cable Connections Drive InstallationParameter System Startup ProcedureSystem Setup Base Casting Assembly Head / Disk Assembly HDADC Spindle Motor Assembly Disk Drive OperationExploded Mechanical View Head Stack Assembly Disk Stack AssemblyVoice Coil Motor and Actuator Latch Assemblies Air Filtration SystemDigital Signal Process and Interface Controller Drive ElectronicsAT Disk Controller 2SID2001 AT Controller Block Diagram Host Interface Control Block Disk Control Block Buffer Control BlockSpinPoint V40 Product Manual Read/Write IC Power ManagementDisk ECC Control Block Frequency SynthesizerAutomatic Gain Control Time Base GeneratorAsymmetry Correction Circuitry ASC Analog Anti-Aliasing Low Pass Filter3Read/Write 88C5200 Servo System Read and Write OperationsRead Channel Firmware Features Write ChannelRead Caching Write Caching Automatic Defect Allocation Defect ManagementMulti-burst ECC Correction SmartBlank Signal Conventions Signal SummaryPhysical Interface Signal Descriptions Dmarq DMA Request DMACK- DMA AcknowledgeIntrq Drive Interrupt IOCS16- Drive 16-bit I/OPDIAG- Passed Diagnostics RESET- Drive ResetIordy I/O Channel Ready SD4 SD8 SD6 SD9 SD5SD3 SD2Drive Host DriveDIR General Logical InterfaceBit Conventions EnvironmentSpinPoint V40 Product Manual 2 I/O Register Address Command Block RegistersControl Block Registers N N N A a aAlternate Status Register 3F6h Control Block Register DescriptionsDrive Address Register 3F7h Device Control Register 3F6hFeatures Register 1F1h Command Block Register DescriptionsError Register 1F1h Data Register 1F0hSector Count Register 1F2h Command Register 1F7hCylinder High Register 1F5h Cylinder Low Register 1F4hBSY Drdy DWF DSC DRQ Corr IDX ERR Status Register 1F7hAt Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Check Power Mode 98h, E5h Execute Device Diagnostics 90hDownload Micro Code 92h Flush Cache E7h Format Track 50hIdentify Device ECh Xxxx Word Content DescriptionCapabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Idle 97h,E3h Idle Immediate 95h,E1hInitialize Device Parameters 91h Read Long 22hwith retry, 23h without retry Read Buffer E4hRead Multiple Command C4h Read Sectors 20hwith retry, 21hwithout retry Read Native Max Address F8hRead Verify Sectors 40hwith retry, 41hwithout retry Recalibrate 1xhSeek 7xh Mode Set Features EFhLBA InputsNormal outputs BSY Drdy DRQ ERRDescription Sleep 99h, E6h Set Multiple Mode C6hSmart disable operation D9h Standby 96h,E2hSmart B0h Smart enable/disable attribute autosave D2h Smart enable operations D8hSmart execute off-line immediate D4h Byte Descriptions Smart read data D0hOff-line data collection capability Value DefinitionSmart read log sector D5h Smart capabilitySmart return status DAh Smart save attribution value D3hStandby Immediate 94h, E0h Standby 96h, E2hWrite Buffer E8h Write DMA CAhWrite Sectors 30hwith retry, 31hwithout retry Write Multiple Command C5hSpinPoint V40 Product Manual Reset Response Error PostingProgramming Requirements BBK Command Error Register Status RegisterSleep mode Power ConditionsStandby mode Idle modeNormal mode Protocol Overview PIO Data in CommandsPIO Data Out Commands PIO Read CommandPIO Read Aborted Command PIO Write Aborted Command PIO Write CommandBSY=0 DRDY=1 BSY=1 BSY=0 DRQ=1 BSY=1 DRQ=0Non-Data Commands DMA Data Transfer Commands Aborted DMA Command Initialize DMA Reset DMA Status BSY=0 BSY=1BSY=1 BSY=0 Register transfers TimingDIOR-/DIOW Write PIO data transfers PIO timing parameters ModeAddr valid See note T1 t2 DIOR-/DIOW DIOR-/DIOW Multiword DMA data transferMultiword DMA timing parameters Mode Initiating an Ultra DMA data in burst Ultra DMA data transfer19Ultra DMA data burst timing requirements Ultra DMA data burst timing requirements5Sustained Ultra DMA data in burst Sustained Ultra DMA data in burst6Host pausing an Ultra DMA data in burst Host pausing an Ultra DMA data in burst7Device terminating an Ultra DMA data in burst 100 Device terminating an Ultra DMA data in burst8Host terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst9Initiating an Ultra DMA data out burst 102 Initiating an Ultra DMA data out burst10Sustained Ultra DMA data out burst Sustained Ultra DMA data out burst11Device pausing an Ultra DMA data out burst 104 Device pausing an Ultra DMA data out burst12Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst13Device terminating an Ultra DMA data out burst 106 Device terminating an Ultra DMA data out burstMaintenance Precautions Service And RepairGeneral Information