Samsung 3.5" hard disk drives manual Sector Count Register 1F2h, Cylinder High Register 1F5h

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DISK DRIVE OPERATION

6.3.4.5Sector Count Register (1F2h)

This register contains the number of sectors of data requested to be transferred on a read or write operation between the host and the drive. If the value in this register is zero, a count of 256 sectors is specified.

If this register is zero at command completion, the command was successful. If not successfully completed, the register contains the number of sectors, which need to be transferred in order to complete the request.

The contents of this register may be defined otherwise on some commands (e.g., Initialize Drive Parameters command, Format Track command).

6.3.4.6Cylinder High Register (1F5h)

In CHS mode this register contains the high order bits of the starting cylinder address for any disk access. In LBA mode this register contains bits 16-23 of the LBA.

At the end of the command, this register is updated to reflect the current disk address. The most significant bits of the cylinder address are loaded into the Cylinder High register.

6.3.4.7Cylinder Low Register (1F4h)

In CHS mode this register contains the low order 8 bits of the starting cylinder address for any disk access. In LBA mode this register contains bits 8-15 of the LBA. At the end of the command, this register is updated to reflect the current disk address.

6.3.4.8Command Register (1F7h)

This register contains the command code being sent to the drive. Command execution begins immediately after this register is written. The executable commands, the command codes, and the necessary parameters for each command are listed in Table 6-4.

6.3.4.9Drive/Head Register (1F6h)

This register contains the drive and head numbers. When executing an Initialize Drive Parameters command, the content of this register defines the number of heads minus 1.

7

1

6

5

4

3

2

1

0

LBA

1

DEV

HS3

HS2

HS1

HS0

 

 

 

 

 

 

 

•DRV is the binary encoded drive select number. When DEV=0, Device 0 is selected. When DEV=1, Device 1 is selected.

•HS3 through HS0 contain the binary coded address of the head to be selected in CHS mode (e.g., if HS3 through HS0 are 0011b, respectively, then head 3 will be selected). HS3 is the most significant bit. In LBA mode this register contains bits 24-27 of the LBA. At command completion, this register is updated to reflect the currently selected disk address.

•LBA is the binary coded address mode select. When L=0, disk addressing is by CHS mode. When L=1, disk addressing is by LBA mode. This bit was set to zero when the ATA drive didn’t support LBA mode

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Contents Spinpoint SpinPoint V40 Product Manual Table of Contents Smart Ervo S Ystem EAD and W Rite O PerationsIrmware F Eatures Timing Programming RequirementsProtocol Overview General Information Maintenance PrecautionsService and Repair 107Table of Figures Page Scope User DefinitionManual Organization Format C/S Commands and MessagesTerminology and Conventions Computer MessageReference Description Key FeaturesIntroduction Hardware Requirements Standards and RegulationsSpecifications Specification SummaryLogical Configurations Physical SpecificationsPerformance Specifications 28.71 Power RequirementsSV6003H SV6014H SV8004H Environmental SpecificationsMtbf POH Reliability SpecificationsSpace Requirements InstallationOrientation Unpacking InstructionsMounting 2Mounting Dimensions in Millimeters 3Mounting-Screw Clearance ClearanceVentilation Cable ConnectorsDC Power Connector AT-Bus Interface ConnectorSpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration 7DC Power Connector and AT-Bus Interface Cable Connections Drive InstallationParameter System Startup ProcedureSystem Setup Disk Drive Operation Head / Disk Assembly HDABase Casting Assembly DC Spindle Motor AssemblyExploded Mechanical View Air Filtration System Disk Stack AssemblyHead Stack Assembly Voice Coil Motor and Actuator Latch AssembliesAT Disk Controller Digital Signal Process and Interface ControllerDrive Electronics 2SID2001 AT Controller Block Diagram Host Interface Control Block Disk Control Block Buffer Control BlockSpinPoint V40 Product Manual Frequency Synthesizer Power ManagementRead/Write IC Disk ECC Control BlockAnalog Anti-Aliasing Low Pass Filter Time Base GeneratorAutomatic Gain Control Asymmetry Correction Circuitry ASC3Read/Write 88C5200 Read Channel Servo SystemRead and Write Operations Read Caching Firmware FeaturesWrite Channel Write Caching Smart Defect ManagementAutomatic Defect Allocation Multi-burst ECC CorrectionBlank Physical Interface Signal ConventionsSignal Summary Signal Descriptions IOCS16- Drive 16-bit I/O DMACK- DMA AcknowledgeDmarq DMA Request Intrq Drive InterruptIordy I/O Channel Ready PDIAG- Passed DiagnosticsRESET- Drive Reset SD2 SD8 SD6 SD9 SD5SD4 SD3Drive Host DriveDIR Environment Logical InterfaceGeneral Bit ConventionsSpinPoint V40 Product Manual N N N A a a Command Block Registers2 I/O Register Address Control Block RegistersDevice Control Register 3F6h Control Block Register DescriptionsAlternate Status Register 3F6h Drive Address Register 3F7hData Register 1F0h Command Block Register DescriptionsFeatures Register 1F1h Error Register 1F1hCylinder Low Register 1F4h Command Register 1F7hSector Count Register 1F2h Cylinder High Register 1F5hBSY Drdy DWF DSC DRQ Corr IDX ERR Status Register 1F7hAt Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Download Micro Code 92h Check Power Mode 98h, E5hExecute Device Diagnostics 90h Identify Device ECh Flush Cache E7hFormat Track 50h Xxxx Word Content DescriptionCapabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Initialize Device Parameters 91h Idle 97h,E3hIdle Immediate 95h,E1h Read Long 22hwith retry, 23h without retry Read Buffer E4hRead Multiple Command C4h Read Sectors 20hwith retry, 21hwithout retry Read Native Max Address F8hSeek 7xh Read Verify Sectors 40hwith retry, 41hwithout retryRecalibrate 1xh Mode Set Features EFhBSY Drdy DRQ ERR InputsLBA Normal outputsDescription Sleep 99h, E6h Set Multiple Mode C6hSmart B0h Smart disable operation D9hStandby 96h,E2h Smart execute off-line immediate D4h Smart enable/disable attribute autosave D2hSmart enable operations D8h Byte Descriptions Smart read data D0hOff-line data collection capability Value DefinitionSmart save attribution value D3h Smart capabilitySmart read log sector D5h Smart return status DAhWrite DMA CAh Standby 96h, E2hStandby Immediate 94h, E0h Write Buffer E8hWrite Sectors 30hwith retry, 31hwithout retry Write Multiple Command C5hSpinPoint V40 Product Manual Programming Requirements Reset ResponseError Posting BBK Command Error Register Status RegisterIdle mode Power ConditionsSleep mode Standby modeNormal mode Protocol Overview PIO Data in CommandsPIO Read Aborted Command PIO Data Out CommandsPIO Read Command BSY=0 DRQ=1 BSY=1 DRQ=0 PIO Write CommandPIO Write Aborted Command BSY=0 DRDY=1 BSY=1Non-Data Commands DMA Data Transfer Commands BSY=1 BSY=0 Aborted DMA Command Initialize DMA Reset DMA StatusBSY=0 BSY=1 Register transfers TimingDIOR-/DIOW Write PIO data transfers PIO timing parameters ModeAddr valid See note T1 t2 DIOR-/DIOW DIOR-/DIOW Multiword DMA data transferMultiword DMA timing parameters Mode Initiating an Ultra DMA data in burst Ultra DMA data transfer19Ultra DMA data burst timing requirements Ultra DMA data burst timing requirements5Sustained Ultra DMA data in burst Sustained Ultra DMA data in burst6Host pausing an Ultra DMA data in burst Host pausing an Ultra DMA data in burst7Device terminating an Ultra DMA data in burst 100 Device terminating an Ultra DMA data in burst8Host terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst9Initiating an Ultra DMA data out burst 102 Initiating an Ultra DMA data out burst10Sustained Ultra DMA data out burst Sustained Ultra DMA data out burst11Device pausing an Ultra DMA data out burst 104 Device pausing an Ultra DMA data out burst12Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst13Device terminating an Ultra DMA data out burst 106 Device terminating an Ultra DMA data out burstGeneral Information Maintenance PrecautionsService And Repair
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