Samsung 3.5" hard disk drives, spinpoint v40 manual Firmware Features, Write Channel, Read Caching

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DISK DRIVE OPERATION

The SID2001 Disk Controller manages the flow of data between the Data Synchronizer on the Read/Write IC and its AT Interface Controller. It also controls data access for the external RAM buffer. The ENDEC of 88C5200 decodes the 32/34 with post-processor format to produce a serial bit stream. This NRZ (Non Return to Zero) serial data is converted to 8-bit bytes.

The Sequencer module identifies the data as belonging to the target sector. After a full sector is read, the SID2001 checks to see if the firmware needs to apply an ECC algorithm to the data.

The Buffer Control section of the SID2001 stores the data in the cache and transmits the data to the AT bus.

5.4.2 The Write Channel

The signal path for the Write Channel follows the reverse order of that for the Read Channel. The host transmits data via the AT bus to the SID2001 Interface Controller. The Buffer Controller section of the SID2001 stores the data in the cache. Because the data is transmitted to the drive at a rate that exceeds the rate at which the drive can write data to the disk, data is stored temporarily in the cache. Thus, the host can present data to the drive at a rate independent of the rate at which the drive can write data to the disk.

Upon correct identification of the target address, the data is shifted to the Sequencer, which generates and appends an error correcting code. The Sequencer then converts the bytes of data to a serial bit stream. The AT controller also generates a preamble field, inserts an address mark, and transmits the data to the ENDEC in the R/W IC where the data is encoded into the 32/34 GCR format and pre-compensates for non-linear transition shift. The amount of write current is set by the SID2001 DSP and Interface/Disk Controller through the serial interface to the preamp.

The SID2001 switches the Preamplifier and Write Driver IC to write mode and selects a head. Once the Preamplifier and Write Driver IC receives a write gate signal, it transmits current reversals to the head, which writes magnetic transitions on the disk

5.5 Firmware Features

This section describes the following firmware features:

•Read Caching

•Write Caching

•Track Skewing

•Defect Management

•Automatic Defect Allocation

•Ten way burst ECC Correction

•SMART (Self-monitoring and reporting technology)

•Dynamic Anti-stiction Algorithm

5.5.1 Read Caching

SpinPoint V40 hard disk drives use a 512KB Read Cache to enhance drive performance and significantly improve system throughput. Use the SET FEATURES command to enable or disable Read Caching. Read caching anticipates host-system requests for data and stores that data for faster future access. When the host requests a certain segment of data, the cache feature utilizes a prefetch strategy to get the data in advance and automatically read and store the following data from the disk into fast RAM. If the host requests this data, the RAM is accessed rather than the disk.

There is a high probability that subsequent data requested will be in the cache, because more than 50 percent of all disk requests are sequential. It takes microseconds rather than milliseconds to retrieve this cached data.

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Contents Spinpoint SpinPoint V40 Product Manual Table of Contents Irmware F Eatures Ervo S Ystem EAD and W Rite O PerationsSmart Protocol Overview Programming RequirementsTiming General Information Maintenance PrecautionsService and Repair 107Table of Figures Page Manual Organization User DefinitionScope Format C/S Commands and MessagesTerminology and Conventions Computer MessageReference Introduction Key FeaturesDescription Hardware Requirements Standards and RegulationsSpecifications Specification SummaryLogical Configurations Physical SpecificationsPerformance Specifications 28.71 Power RequirementsSV6003H SV6014H SV8004H Environmental SpecificationsMtbf POH Reliability SpecificationsSpace Requirements InstallationMounting Unpacking InstructionsOrientation 2Mounting Dimensions in Millimeters 3Mounting-Screw Clearance ClearanceVentilation Cable ConnectorsDC Power Connector AT-Bus Interface ConnectorSpinPoint V40 Product Manual Jumper Block Configurations Options for Jumper Block Configuration 7DC Power Connector and AT-Bus Interface Cable Connections Drive InstallationParameter System Startup ProcedureSystem Setup Disk Drive Operation Head / Disk Assembly HDABase Casting Assembly DC Spindle Motor AssemblyExploded Mechanical View Air Filtration System Disk Stack AssemblyHead Stack Assembly Voice Coil Motor and Actuator Latch AssembliesDrive Electronics Digital Signal Process and Interface ControllerAT Disk Controller 2SID2001 AT Controller Block Diagram Host Interface Control Block Disk Control Block Buffer Control BlockSpinPoint V40 Product Manual Frequency Synthesizer Power ManagementRead/Write IC Disk ECC Control BlockAnalog Anti-Aliasing Low Pass Filter Time Base GeneratorAutomatic Gain Control Asymmetry Correction Circuitry ASC3Read/Write 88C5200 Read and Write Operations Servo SystemRead Channel Write Channel Firmware FeaturesRead Caching Write Caching Smart Defect ManagementAutomatic Defect Allocation Multi-burst ECC CorrectionBlank Signal Summary Signal ConventionsPhysical Interface Signal Descriptions IOCS16- Drive 16-bit I/O DMACK- DMA AcknowledgeDmarq DMA Request Intrq Drive InterruptRESET- Drive Reset PDIAG- Passed DiagnosticsIordy I/O Channel Ready SD2 SD8 SD6 SD9 SD5SD4 SD3Drive Host DriveDIR Environment Logical InterfaceGeneral Bit ConventionsSpinPoint V40 Product Manual N N N A a a Command Block Registers2 I/O Register Address Control Block RegistersDevice Control Register 3F6h Control Block Register DescriptionsAlternate Status Register 3F6h Drive Address Register 3F7hData Register 1F0h Command Block Register DescriptionsFeatures Register 1F1h Error Register 1F1hCylinder Low Register 1F4h Command Register 1F7hSector Count Register 1F2h Cylinder High Register 1F5hBSY Drdy DWF DSC DRQ Corr IDX ERR Status Register 1F7hAt Command Register Descriptions Command Parameter Used SpinPoint V40 Product Manual Execute Device Diagnostics 90h Check Power Mode 98h, E5hDownload Micro Code 92h Format Track 50h Flush Cache E7hIdentify Device ECh Xxxx Word Content DescriptionCapabilities Command set supported 95-128 0000h Reserved 129-159 Vendor specific 160-255 Idle Immediate 95h,E1h Idle 97h,E3hInitialize Device Parameters 91h Read Long 22hwith retry, 23h without retry Read Buffer E4hRead Multiple Command C4h Read Sectors 20hwith retry, 21hwithout retry Read Native Max Address F8hRecalibrate 1xh Read Verify Sectors 40hwith retry, 41hwithout retrySeek 7xh Mode Set Features EFhBSY Drdy DRQ ERR InputsLBA Normal outputsDescription Sleep 99h, E6h Set Multiple Mode C6hStandby 96h,E2h Smart disable operation D9hSmart B0h Smart enable operations D8h Smart enable/disable attribute autosave D2hSmart execute off-line immediate D4h Byte Descriptions Smart read data D0hOff-line data collection capability Value DefinitionSmart save attribution value D3h Smart capabilitySmart read log sector D5h Smart return status DAhWrite DMA CAh Standby 96h, E2hStandby Immediate 94h, E0h Write Buffer E8hWrite Sectors 30hwith retry, 31hwithout retry Write Multiple Command C5hSpinPoint V40 Product Manual Error Posting Reset ResponseProgramming Requirements BBK Command Error Register Status RegisterIdle mode Power ConditionsSleep mode Standby modeNormal mode Protocol Overview PIO Data in CommandsPIO Read Command PIO Data Out CommandsPIO Read Aborted Command BSY=0 DRQ=1 BSY=1 DRQ=0 PIO Write CommandPIO Write Aborted Command BSY=0 DRDY=1 BSY=1Non-Data Commands DMA Data Transfer Commands BSY=0 BSY=1 Aborted DMA Command Initialize DMA Reset DMA StatusBSY=1 BSY=0 Register transfers TimingDIOR-/DIOW Write PIO data transfers PIO timing parameters ModeAddr valid See note T1 t2 DIOR-/DIOW DIOR-/DIOW Multiword DMA data transferMultiword DMA timing parameters Mode Initiating an Ultra DMA data in burst Ultra DMA data transfer19Ultra DMA data burst timing requirements Ultra DMA data burst timing requirements5Sustained Ultra DMA data in burst Sustained Ultra DMA data in burst6Host pausing an Ultra DMA data in burst Host pausing an Ultra DMA data in burst7Device terminating an Ultra DMA data in burst 100 Device terminating an Ultra DMA data in burst8Host terminating an Ultra DMA data in burst Host terminating an Ultra DMA data in burst9Initiating an Ultra DMA data out burst 102 Initiating an Ultra DMA data out burst10Sustained Ultra DMA data out burst Sustained Ultra DMA data out burst11Device pausing an Ultra DMA data out burst 104 Device pausing an Ultra DMA data out burst12Host terminating an Ultra DMA data out burst Host terminating an Ultra DMA data out burst13Device terminating an Ultra DMA data out burst 106 Device terminating an Ultra DMA data out burstService And Repair Maintenance PrecautionsGeneral Information
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